3D Magnetic Memory Stack With SOT Writing and MTJ Readout
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Solution Overview
Problem
Existing magnetic memory technologies are limited by planar configurations, which restrict achievable memory density and hinder their application beyond embedded memory technology.
Innovation Solution
A 3D magnetic memory device architecture utilizing a stack of alternating dielectric and silicon-based layers with a magnetic material channel extending through, featuring pinning sites for magnetic bits and employing spin-orbit-torque (SOT) for writing and magnetic tunnel junction (MTJ) for reading, allowing information storage and retrieval in three dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar configuration is used for magnetic memory devices, then manufacturing is easier and device structure is simpler, but memory density is limited and cannot achieve high-capacity storage
Solution Approach 1:
The patent transitions from planar 2D configuration to three-dimensional vertical stacking architecture. Multiple magnetic tunnel junctions are stacked vertically with conductive layers in between, enabling memory density improvement by utilizing the third dimension while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The patent implements nested structures where magnetic tunnel junctions are stacked within each other, with each junction consisting of multiple ultra-thin layers nested sequentially. The conductive layers are nested between the magnetic tunnel junctions, creating a compact vertical integration that maximizes memory density
2Quantity of substance
If 3D stacking architecture is implemented to increase memory density, then memory density is significantly improved, but device complexity increases and manufacturing becomes more difficult
Solution Approach 1:
The conductive layers serve multiple functions: they provide electrical connection between stacked magnetic tunnel junctions, act as spin-orbit torque tracks for writing magnetic bits, and enable current routing. This multi-functionality reduces the need for separate dedicated structures, thereby managing device complexity
Solution Approach 2:
The patent merges the write mechanism (spin-orbit torque track) with the interconnect structure (conductive layer between stacked junctions). The same conductive layer that provides electrical connection also functions as the SOT track for writing operations, reducing overall device complexity
3Manufacturing precision
If physical vapor deposition is used to create MRAM stack with over 20 ultra-thin layers, then manufacturing precision is achieved, but the process is complex and limited to planar implementation
Solution Approach 1:
The patent extends the PVD-based ultra-thin layer deposition process from planar to vertical 3D stacking. The same deposition techniques are used to create the stacked architecture, maintaining manufacturing precision while enabling three-dimensional implementation through repeated cyclic deposition of magnetic and conductive layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly increases memory density and enables efficient storage and retrieval of magnetic bits, while maintaining fast operation speeds and endurance.
Implementation Method 1
A 3D magnetic memory device architecture utilizing a stack of alternating dielectric and silicon-based layers with a magnetic material channel extending through, featuring pinning sites for magnetic bits and employing spin-orbit-torque (SOT) for writing
Implementation Method 2
The tunnel magnetoresistance (TMR) effect provides different resistance states depending on whether the magnetizations of the free layer and reference layer are aligned in a parallel or antiparallel
Data Source
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AI summary
This disclosure relates to a 3D magnetic memory device (10). The device comprises a stack (11) with a plurality of dielectric layers (11a) and silicon-based layers (11b) alternatingly arranged one on the other. A magnetic material channel (12) is formed through the stack and extends through each layer of the stack. The channel has a first diameter where it extends through a silicon-based layer and a second diameter where it extends through a dielectric layer. A plurality of pinning sites defined by the layers of the stack is formed in the channel, each pinning site being configured to store one magnetic bit. The device further comprises a first metallic layer (13) arranged on a first end of the channel and on the last layer of the stack, a magnetic tunnel junction (MTJ) (14) arranged on the first metallic layer, and a first electrode (15) arranged on the first metallic layer at a distance to the MTJ. In addition, either the first metallic layer is configured as a spin-orbit-torque (SOT) track, or the device comprises a second metallic layer (16) configured as a SOT track. In the latter case, a second end of the channel and the first layer of the stack are arranged on the second metallic layer.