Digital Storage TRIZ Cases
- Shared-Selector Resistive Memory Assembly for Low-Leakage Density
A shared selector layer lets parallel resistive memory stacks suppress leakage current while preserving chip area and read/write stability.
- Selectable Wordline Driver with Centralized Local Wordline Control
Centralized voltage generation drives selected local wordlines from a global wordline, cutting driver footprint, contacts, and 3D DRAM density loss.
- MRAM Read Circuit Using Source-Line Bias to Cut Leakage
Raising source-line voltage above the bit line uses NMOS body effect to suppress leakage and improve MRAM read-state discrimination.
- Flash Memory Wear Leveling Using Sector Error Flags
Sector flags track bit correction and data presence so flash memory can move critical data to less worn sectors and improve boot data reliability.
- Multi-Bit Memory Cell Layout to Prevent Half-Selected Writes
Separate column selection from write word lines to stop half-selected data flips, cut write current, and save memory cell area.
- CXL Memory Controller Refresh Logic for Row Hammer Patterns
Pattern-based row hammer detection triggers targeted DRAM refresh, protecting data integrity without adding more registers or reducing density.
- DRAM Bit Line Pre-Charge Circuit With Stable Low-Noise Step-Down Bias
Adjustable p- and n-threshold biasing stabilizes DRAM bit line pre-charge at half supply voltage while reducing ripple and switching noise.
- Cross-Point Memory Cell Structure With Vertical Selector Layer
A vertical selector layer around the electrode limits redeposition and surface roughness, protecting variable resistance layers in dense cross-point arrays.
- Combinatory Logic Decoding for Multi-Level Memory Cells
Sequential sense-amplifier reads and combinatory logic decode multi-level memory cells to raise bit density without enlarging the array.
- Memory Read Timing Control for Lower Precharge Power
A sensing amplifier and controller shorten read periods for nearer memory cells, cutting unnecessary precharge power while preserving read reliability.
- Series MTJ Memory Cell Layout for Polymorphic Storage States
Using two MTJs in series with different current directions and magnitudes enables multi-resistance memory states that raise storage density.
- Input Buffer Offset Adjustment for Accurate Inversion Point Detection
A switched test and main input buffer adjusts offset voltage against VREF, reducing inversion point errors in low-voltage semiconductor memory.
- 3D Memory Array Layout With Staggered Contacts and Lower Capacitance
Staggered contacts and serpentine trench isolation raise 3D memory density while reducing inter-floor capacitance and voltage leakage.
- 3D Magnetic Memory Stack With SOT Writing and MTJ Readout
Vertical pinning sites in a magnetic channel boost memory density, while SOT writes bits and an MTJ reads them efficiently.
- Shared Pass Transistor Memory Circuit for Compact Layout
A shared pass transistor handles read/write and idle-stage precharge to shrink memory circuit layout while limiting noise and matching issues.
- Ferroelectric Memory Voltage Control for Lower Refresh Interference
Two-phase voltage control lowers interference on unselected ferroelectric memory cells, reducing refresh frequency while preserving the read window.