Sense Amplifier Control Circuit for ON-Resistance Offset Cancellation
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Solution Overview
Problem
Existing memory devices face challenges in accurately determining stored data due to deviations in potential levels caused by differences in ON resistance between transistors within the sense amplifier circuit, leading to unreliable data sensing.
Innovation Solution
Implementing a sense amplifier control circuit that includes offset cancellation and charge sharing mechanisms to equalize and compensate for differences in ON resistance between transistors, ensuring accurate potential levels for data determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sense amplifier circuits are used without offset cancellation, then the circuit structure remains simple, but potential level deviations occur due to ON resistance differences between transistors, leading to inaccurate data determination
Solution Approach 1:
The patent applies preliminary action by performing offset cancellation before the main data sensing operation. The sense amplifier circuit first equalizes the potential levels between complementary bit lines using the offset cancellation circuit, which compensates for resistance differences in advance. This preliminary equalization ensures that subsequent data sensing occurs from a balanced baseline, improving measurement precision without requiring fundamental changes to the overall circuit architecture.
Solution Approach 2:
The patent introduces an intermediary offset cancellation circuit that mediates between the memory cell array and the main sense amplifier. This intermediary circuit includes compensation transistors and control circuits that actively balance the potential levels by counteracting the effects of ON resistance variations. The intermediary circuit acts as a buffer that prepares the signal conditions before they reach the main data sensing path, thereby improving accuracy while maintaining relative structural simplicity.
2Reliability
If offset cancellation circuit is implemented, then potential level deviations are compensated and data determination reliability improves, but the circuit structure becomes more complex with additional transistors and control signals
Solution Approach 1:
The patent utilizes parameter changes by dynamically adjusting the resistance characteristics of compensation transistors through controlled potential changes. The offset cancellation circuit modifies the electrical parameters (potential levels, resistance values) of its components in response to detected imbalances, actively compensating for manufacturing variations and operational drifts. This dynamic parameter adjustment enhances reliability by adapting to actual circuit conditions rather than relying on fixed design values.
Solution Approach 2:
The patent implements feedback mechanisms where the sense amplifier control circuit continuously monitors potential level differences between complementary bit lines and adjusts the offset cancellation circuit accordingly. The control circuit uses feedback signals to modulate the compensation transistors, creating a closed-loop system that automatically corrects imbalances. This feedback approach ensures high data determination reliability by continuously maintaining optimal operating conditions despite variations in transistor characteristics.
Data Source
AI summary
A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.