Ferroelectric Memory Cell Layout With Overlapping Capacitors
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Solution Overview
Problem
Existing ferroelectric memories face challenges in achieving high capacitance values without compromising memory cell density or increasing the occupied area, leading to issues with data retention reliability and power consumption.
Innovation Solution
The semiconductor device incorporates first and second capacitors with overlapping regions and transistors, utilizing ferroelectric materials like hafnium and zirconium, to enhance capacitance while maintaining a compact design and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the dielectric is reduced to increase capacitance value, then the capacitance value increases, but the remanent polarization decreases making data retention unreliable
Solution Approach 1:
The patent changes the material parameter of the dielectric from conventional materials to ferroelectric materials (such as Pb(Zr,Ti)O3, Pb(Mg3Nb2/3)O3-PbTiO3, or HfO2), which fundamentally alters the polarization characteristics. This allows achieving high remanent polarization even at reduced thicknesses, resolving the contradiction between capacitance increase and data retention reliability.
2Quantity of substance
If the area of the capacitor is increased to increase capacitance value, then the capacitance value increases, but the occupied area of memory elements increases reducing memory density
Solution Approach 1:
By changing the dielectric material to ferroelectric materials with high remanent polarization, the patent achieves high capacitance values within the same physical area. This eliminates the need to increase capacitor area to boost capacitance, thereby maintaining high memory density while achieving reliable data retention.
3Quantity of substance
If conventional dielectric materials are used to achieve high capacitance, then the capacitance value increases, but the remanent polarization decreases making it difficult to retain written data accurately
Solution Approach 1:
The patent employs composite ferroelectric materials such as Pb(Zr,Ti)O3, Pb(Mg3Nb2/3)O3-PbTiO3, and HfO2, which combine the benefits of high capacitance and high remanent polarization. These composite materials specifically engineered to simultaneously provide both high capacitance values and high remanent polarization, resolving the fundamental contradiction between these two parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a memory device with high memory capacity, low power consumption, and reliable data retention, occupying a small area, thus addressing the limitations of traditional ferroelectric memory designs.
Implementation Method 1
data writing and reading operations are performed by utilizing polarization reversal of a ferroelectric
Implementation Method 2
the remanent polarization of the ferroelectric needs to be increased
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of memory cells each including a transistor and a capacitor, and capacitors included in adjacent memory cells are provided to overlap with each other. A first capacitor included in a first memory cell is provided so as to partly overlap with a second memory cell adjacent to the first memory cell. A second capacitor included in a second memory cell and the first capacitor are provided over different layers. The second capacitor is provided so as to partly overlap with the first memory cell. The first capacitor and the second capacitor include a region where they overlap with each other. The first and second capacitors include a ferroelectric. The ferroelectric preferably includes hafnium, zirconium, or at least one element selected from Group III-V elements. The transistor preferably includes an oxide semiconductor in a semiconductor layer where a channel is formed.