Latency Circuit Dynamic Clock Division for SDRAM Stability
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Solution Overview
Problem
Conventional latency circuits in semiconductor memory devices face challenges in generating stable latency signals at varying clock frequencies and environmental conditions, leading to incorrect clock cycle counting and data output issues.
Innovation Solution
A latency circuit capable of selectively using 1-division or 2-division output clock signals based on CAS latency, incorporating a latency control clock generator and signal generator with shift registers and regulators to ensure stable latching of internal read command signals, even at high frequencies and low frequency operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2-divided output clock signal is used to generate the latency signal, then the latency signal can be stably generated at high frequency external clocks, but a lock cycle loss occurs during low frequency operations such as CAS latency 5
Solution Approach 1:
The latency circuit dynamically adjusts the clock division ratio based on the CAS latency setting. When operating at high frequencies, it uses 2-division to maintain stability; when operating at low frequencies like CAS latency 5, it switches to 1-division to prevent lock cycle loss. This dynamic adaptation allows the circuit to optimize performance for different operating conditions.
2Speed
If the external clock frequency increases, then the operating speed of the SDRAM increases, but the timing margin between the internal read command signal and the output clock signal decreases
Solution Approach 1:
The patent introduces an intermediate latency control mechanism that uses a programmable counter and control logic to precisely manage the timing relationship between the internal read command signal and the output clock signal. This intermediary control structure allows the circuit to maintain adequate timing margins even at high clock frequencies by dynamically adjusting the latency signal generation based on the actual timing conditions.
3Measurement precision
If the pulse width of the internal read command signal decreases at high frequencies, then the clock cycle counting accuracy improves, but the internal read command signal cannot be normally latched
Solution Approach 1:
The circuit performs preliminary actions by generating the latency signal in advance based on the CAS latency setting before the actual data read operation commences. This preliminary signal generation allows the system to prepare the timing configuration ahead of time, ensuring that when the internal read command signal arrives (even with reduced pulse width at high frequencies), the latching circuit is already properly configured to capture it reliably.
Data Source
AI summary
A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.