3D Memory Array Layout With Staggered Contacts and Lower Capacitance
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Solution Overview
Problem
Existing 3-D memory arrays face challenges in achieving high memory cell density and reducing capacitance between adjacent floors while maintaining effective voltage application.
Innovation Solution
A 3-D memory array design featuring a staggered arrangement of conductive contacts and serpentine-shaped trenches that bifurcate conductive planes, combined with chalcogenide storage elements and orthogonal conductive pillars, allowing for increased memory cell density and reduced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3-D memory array design is used, then manufacturing process is simpler, but memory cell density is lower and capacitance between floors is higher
Solution Approach 1:
The conductive planes are segmented into multiple sections by serpentine-shaped trenches, creating isolated regions that reduce capacitance between adjacent floors. The conductive contacts are arranged in a staggered pattern rather than a regular grid, dividing the array into interleaved sets that can be independently addressed, thereby increasing density without proportionally increasing complexity.
Solution Approach 2:
The patent introduces a vertical dimension to the conductive contact arrangement by staggering contacts at different heights across multiple floors. This 3-D staggering pattern allows more contacts to be packed within the same lateral footprint while maintaining electrical isolation, effectively increasing memory cell density without requiring a proportional increase in lateral area or structural complexity.
2Quantity of substance
If conductive planes are closely spaced to increase density, then memory cell density increases, but capacitance between adjacent floors increases
Solution Approach 1:
Serpentine-shaped trenches partition each conductive plane into multiple isolated segments. This segmentation reduces the overlapping area between adjacent conductive planes on different floors, thereby reducing parasitic capacitance even when planes are closely spaced to achieve high density. The segmented structure allows electric field confinement within each segment, minimizing inter-floor capacitive coupling.
Solution Approach 2:
The serpentine trenches act as intermediary insulating structures between adjacent conductive planes. These trenches, filled with insulating material, serve as mediators that physically separate and electrically isolate the conductive planes while maintaining close spacing for high density. The intermediary structures prevent direct capacitive coupling between floors, enabling high-density placement without suffering from excessive inter-floor capacitance.
3Measurement precision
If voltage is applied to select specific memory cells, then data access precision improves, but voltage leakage to adjacent cells increases
Solution Approach 1:
The staggered arrangement of conductive contacts creates isolated voltage application paths. When voltage is applied to a specific contact, the segmented structure ensures that the electric field is confined to the intended memory cell region. The interleaved pattern of contacts from different floors prevents voltage spreading to adjacent cells, as each contact is spatially separated from its neighbors both laterally and vertically, thereby improving voltage application precision and reducing leakage.
4Quantity of substance
If more conductive contacts are added to increase density, then memory cell density increases, but array structure complexity increases
Solution Approach 1:
The conductive contacts are arranged in an asymmetric staggered pattern rather than a symmetric regular grid. This asymmetric arrangement allows more contacts to be packed into the same area by optimizing their spatial distribution. The staggered pattern creates an irregular, non-uniform structure that increases density while the repeating unit cell pattern maintains manufacturability and addresses decodability, preventing complexity from becoming unmanageable.
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.