3D Ferroelectric Memory Array for Compute-in-Memory
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Solution Overview
Problem
Conventional compute-in-memory systems face limitations in processing speed due to increasing data transfer rates and associated power dissipation, particularly in large-scale computational systems like convolutional neural networks, where data transfer latency and power consumption are significant factors.
Innovation Solution
A computing device with a three-dimensional memory array module in the BEOL region of an integrated circuit, utilizing one-transistor ferroelectric random-access memory cells, where weight values are stored and input signals are applied to perform simultaneous multiply-accumulate operations with minimal latency and power consumption, leveraging a circuitry structure that extends in multiple dimensions for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer rates are increased to improve processing speed, then computational throughput is improved, but power dissipation increases
Solution Approach 1:
The patent transitions from conventional two-dimensional memory arrays to three-dimensional crossbar architectures, adding a vertical dimension to data processing. This enables simultaneous multiply-accumulate operations across multiple layers, dramatically improving processing speed while keeping data resident in memory to avoid power-intensive data transfers.
Solution Approach 2:
The patent merges storage and computation functions into a single integrated memory structure. By embedding computational capabilities directly within the memory array, data can be processed in-place without being transferred to separate processing units, thereby improving processing speed while eliminating the power consumption associated with data movement.
2Adaptability or versatility
If data is moved between main RAM and data store for computation, then processing flexibility is maintained, but data transfer latency increases
Solution Approach 1:
The patent segments the computational process into distributed operations across multiple memory cells and layers. Each memory cell performs local computations on stored data, enabling parallel processing throughout the three-dimensional array. This segmentation allows flexible data processing while eliminating the need for centralized data transfer, thereby reducing latency.
Solution Approach 2:
The memory structure performs computations autonomously using the stored data itself as both input and storage medium. The crossbar architecture enables each memory cell to self-configure for specific computations by selectively activating connections between rows and columns, providing processing flexibility without external data movement and eliminating transfer latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables real-time data analysis and decision-making by reducing computational latency and power dissipation, enhancing the performance of in-memory computing systems, particularly in resource-constrained environments.
Implementation Method 1
utilizing one-transistor ferroelectric random-access memory cells
Data Source
AI summary
In some embodiments, an integrated circuit (IC) device includes an active semiconductor layer, a circuitry formed within the active semiconductor layer, a region including conductive layers formed in a back-end-of-line (BEOL) layer above the active semiconductor layer, and a memory module formed in the BEOL layer. The memory device includes a three-dimensional array of memory cells, each adapted to store a weight value, and adapted to generate at each memory cell a signal indicative of a product between the stored weight value and an input signal applied to the memory cell. The memory module is further adapted to transmit the product signals from the memory cell simultaneously in the direction of the active semiconductor layer.