Semiconductor Synchronization Buffer Size Reduction
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Solution Overview
Problem
The existing semiconductor apparatus designs face challenges in reducing circuit size due to the increased capacity of synchronization buffers and data buffers, which grow in proportion to frequency differences and data widths, making it difficult to manage resource usage effectively.
Innovation Solution
The proposed semiconductor apparatus employs a synchronization method that stores data write pointers in a FIFO buffer, synchronizes validation signals, and uses a smaller synchronization buffer to manage data transfer between IPs operating at different frequencies, reducing the overall circuit size by optimizing the storage and processing of data write pointers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronization buffer is used to absorb frequency differences between IPs, then data transfer synchronization is achieved, but the circuit size increases
Solution Approach 1:
The patent extracts the data write pointer from the synchronization buffer, separating the pointer management function from the data storage function. This allows the synchronization buffer to store only pointers (requiring fewer resources) while data is stored in a separate data buffer, thereby reducing the circuit size while maintaining synchronization reliability
Solution Approach 2:
The patent segments the buffer system into two independent buffers: a synchronization buffer for storing data write pointers and a data buffer for storing actual data. This segmentation allows each buffer to be optimized independently, with the synchronization buffer requiring minimal size since it only stores pointer information, thus reducing overall circuit size while maintaining synchronization functionality
2Adaptability or versatility
If the capacity of synchronization buffer and data buffer is increased to handle larger frequency differences and data widths, then synchronization capability is improved, but resource usage increases
Solution Approach 1:
The patent extracts the pointer management function from data storage, allowing the synchronization buffer to accommodate larger frequency differences and data widths by storing only pointers rather than full data. This extraction enables the system to handle greater synchronization demands while using fewer resources since pointer storage requires minimal capacity regardless of data width
Solution Approach 2:
The patent changes the parameter being stored in the synchronization buffer from full data to data write pointers. This parameter change allows the buffer capacity to remain small while the system's adaptability to handle larger frequency differences and data widths is maintained through the pointer mechanism, which can reference data in the separate data buffer
Data Source
AI summary
Data is synchronized when transmitted from a circuit operated at first frequency to another circuit operated at second frequency. A synchronization method includes storing data write pointers in a line, storing data input from a source at first frequency at a location in a data buffer designated by the write pointer at one end of the line, taking out the write pointer at the one end from the line to store it in the synchronization buffer, synchronizing a validation signal input from the input source at first frequency to second frequency, reading out the write pointer stored in the synchronization buffer when the validation signal is synchronized, adding completion information that indicates completion of synchronization to the data stored at the location in the data buffer designated by the read out write pointer, and reading out, from the data buffer, the data to which the completion information is added.


