Memory Cell Bias Circuit for Read Disturb Reduction

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining the threshold voltage stability of memory cells due to repeated read operations, which can alter their resistance states.

Innovation Solution

The semiconductor device incorporates a read disturbance reduction circuit with an inductor to generate undershoot on the current path after read operations, reversing the current direction to restore the threshold voltage of memory cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If repeated read operations are performed on memory cells, then data can be accessed continuously, but the threshold voltage of memory cells changes due to read disturbance

Engineering Contradiction:
Improvecontinuous data access capabilityVSAvoidthreshold voltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by introducing a read disturbance reduction circuit that generates an opposite current to counteract the threshold voltage change caused by read operations. Before the threshold voltage can significantly deviate from its intended state, the circuit detects the disturbance and applies a compensating current in the opposite direction to prevent the harmful effect from accumulating.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent implements feedback by using a read disturbance reduction circuit that monitors the effect of read operations on memory cell threshold voltage and dynamically adjusts the compensating current accordingly. The circuit receives control signals based on the detected threshold voltage change and modulates the opposite current to maintain threshold voltage stability, creating a closed-loop control system.

Inventive Principle:
Principle #23Feedback

2Reliability

If a read disturbance reduction circuit is added to counteract threshold voltage changes, then threshold voltage stability is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses an intermediary approach by introducing a dedicated read disturbance reduction circuit that acts as a mediator between the sense amplifier and the memory cell. This intermediate circuit processes the read disturbance signal and generates the compensating opposite current, isolating the memory cell from direct exposure to read disturbance while maintaining stability through controlled intervention.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Prevents the threshold voltage of memory cells from being changed due to repeated read operations, ensuring stable resistance states.

Implementation Method 1

a read disturbance reduction circuit configured to generate undershoot on the current path when the sense amplifier determines the state of the memory cell

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS12537055B2Semiconductor device
Publication Date: 2026.01.27 SK HYNIX INC
  • US12537055B2 patent drawing
  • US12537055B2 patent drawing
  • US12537055B2 patent drawing

AI summary

A semiconductor device may include a read disturb reduction circuit, a first selection switch that is turned on based on a bit line selection signal, a second selection switch that that is turned on based on a word line selection signal, a memory cell electrically connected between the first selection switch and the second selection switch, a first bias voltage generation circuit configured to provide a first bias voltage to the memory cell through the first selection switch, a second bias voltage generation circuit configured to provide a second bias voltage to the memory cell through the first selection switch, a third bias voltage generation circuit configured to provide a third bias voltage to the memory cell through the second selection switch, and a connection switch configured to electrically connect or separate the read disturbance reduction circuit and the second selection switch.