Memory Timing Training With Majority Decision Sampling
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Solution Overview
Problem
Memory devices face challenges in accurately sampling data signals due to temporal misalignment between clock and data signals, which can occur due to drift caused by temperature changes, voltage fluctuations, and noise, leading to incorrect data sampling.
Innovation Solution
Implementing a majority decision mechanism that uses multiple data samples and clock signals to select the correct data sample and adjust timing to achieve alignment, allowing for accurate data sampling without interrupting ongoing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single clock signal is used for data sampling, then the device complexity is low, but the data sampling accuracy deteriorates due to temporal misalignment
Solution Approach 1:
The patent divides the single sampling operation into multiple parallel sampling operations using multiple clock signals (first clock signal and second clock signal). This segmentation allows the system to capture data at different time points, improving the likelihood of obtaining accurate samples despite timing drift between clock and data signals.
Solution Approach 2:
The patent implements a feedback mechanism where the system determines whether obtained data samples are correct and uses this information to adjust future sampling operations. The feedback loop enables the system to learn from past sampling results and improve accuracy over time by selecting appropriate clock signals based on observed timing relationships.
2Measurement precision
If multiple data samples are taken with different clock signals, then the data sampling accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent designs the sampling circuit to handle multiple clock signals and multiple data samples using a unified architecture. The same sampling circuitry is reused across different clock domains, and a single determination mechanism evaluates all samples to identify correct ones. This multi-functional design improves sampling accuracy without proportionally increasing device complexity.
Solution Approach 2:
The patent changes the timing parameters of clock signals to create multiple sampling opportunities. By varying the phase or frequency of clock signals, the system captures data at different moments in the data signal's transition window, increasing the probability of obtaining valid samples while maintaining a relatively simple determination logic.
3Measurement precision
If timing adjustment is performed to align clock and data signals, then the data sampling accuracy is improved, but the productivity decreases due to potential operation interruptions
Solution Approach 1:
The patent performs timing determination and clock signal selection in advance, before actual data sampling operations. By pre-establishing the relationship between clock signals and data signals, the system can immediately begin accurate sampling without interrupting ongoing operations. This preliminary action eliminates the need to pause productivity for timing adjustments.
Solution Approach 2:
The system autonomously determines the correctness of data samples and selects appropriate clock signals without external intervention or operation interruption. The self-service mechanism continuously monitors and adjusts timing relationships, ensuring accurate sampling while maintaining uninterrupted data operations. This eliminates the trade-off between timing alignment and productivity.
Data Source
AI summary
Embodiments for improving timing in memory devices are disclosed. A device may include circuitry configured to sample a data signal according to a clock signal to obtain a data sample and sample the data signal according to at least one additional clock signal to obtain at least one additional data sample. The circuitry may also be configured to compare the data sample to the at least one additional data sample and increment or decrement a counter in response to the comparison. Further, the circuitry may be configured to adjust one or more of the clock signal or the additional clock signal based on a value of the counter. Associated methods and systems are also disclosed.