DRAM Read Register Timing with Equalized Control Signal Paths
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Solution Overview
Problem
The timing mismatch between asynchronous sampling signals and global data in dynamic random access memory (DRAM) due to process variations and temperature fluctuations leads to sampling errors, affecting data read accuracy.
Innovation Solution
Implementing a control signal synthesis circuit that equalizes the path lengths for control signals from multiple memory banks to a read register, ensuring synchronized data sampling through an overall control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous sampling signals are used in DRAM, then data read speed is improved, but timing mismatch occurs due to process variations and temperature fluctuations leading to sampling errors
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the asynchronous sampling signal generation unit and the read register. This delay circuit receives the asynchronous sampling signal and outputs a delayed version, acting as a mediator to adjust the timing relationship between control signals and global data, thereby eliminating timing mismatch while preserving the speed advantage of asynchronous sampling
Solution Approach 2:
The patent changes the time parameter of the sampling signal by introducing a controllable delay. The delay circuit adjusts the timing parameter of the asynchronous sampling signal to match the arrival time of global data at the read register, resolving the timing mismatch caused by process variations and temperature fluctuations without changing the fundamental asynchronous sampling mechanism
2Device complexity
If path lengths for control signals from multiple memory banks are not equalized, then device complexity is reduced, but timing mismatch occurs affecting data read accuracy
Solution Approach 1:
The patent applies local quality adjustment by introducing delay circuits selectively at specific locations in the signal path. Instead of equalizing all path lengths globally, delay circuits are placed locally at input terminals of the read register to compensate for path length differences, thereby achieving timing synchronization without redesigning the entire signal distribution network
Solution Approach 2:
The delay circuit performs preliminary action by advancing or delaying the control signal before it reaches the read register. This preliminary timing adjustment ensures that control signals from different memory banks arrive at the register simultaneously, preventing timing mismatch before the actual sampling operation occurs
Data Source
AI summary
Memories, operation methods and memory systems are provided. An example memory includes M memory banks and a peripheral circuit including a control signal synthesis circuit and a first read register. The control signal synthesis circuit includes input terminals and a first output terminal. each input terminal is connected with one corresponding memory bank and the first output terminal is connected with the first read register. The control signal synthesis circuit is configured to receive control signals through input terminals and output an overall control signal through the first output terminal. A path from each input terminal to the first output terminal in the control signal synthesis circuit has a same length. The first read register is configured to receive the overall control signal and data read from at least one of the M memory banks and output the read data based on the overall control signal.