Refresh Counter Circuit Redundancy Test Address Rearrangement
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Solution Overview
Problem
In DRAM devices, the refresh address counter circuit wastes time and resources when refreshing a redundancy area, as it must perform unnecessary counting operations due to the narrower address range of the redundancy area compared to the normal area, leading to increased test time.
Innovation Solution
The refresh counter circuit rearranges its output to prioritize addresses for the redundancy area, placing them on lower-order bits, thereby generating only necessary addresses for the redundancy area during testing, reducing the inclusion of unnecessary normal area addresses and shortening the test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a refresh address counter circuit designed for normal area is used to refresh redundancy area, then the circuit can perform refresh operations, but it performs unnecessary counting operations for normal area addresses, increasing test time
Solution Approach 1:
The refresh counter circuit dynamically changes its counting behavior based on the test mode. In redundancy test mode, the counter is configured to count only up to the maximum redundancy address (e.g., 64 addresses), while in normal operation mode, it counts across the full address range. This dynamic reconfiguration eliminates unnecessary counting cycles during redundancy testing, directly resolving the time loss contradiction.
Solution Approach 2:
The invention changes the counting parameter (count limit) of the refresh counter based on the operational mode. By detecting whether a redundancy test is being performed, the system adjusts the counter's maximum value parameter - setting it to the redundancy area size (64) during tests versus the full memory size during normal operation. This parameter adaptation allows the same hardware to efficiently handle both scenarios without waste.
2Productivity
If the refresh counter performs counting operations for the full address range, then it can address all memory areas, but it wastes cycles counting normal area addresses when only redundancy area needs testing
Solution Approach 1:
The invention extracts and isolates the redundancy area testing function from the full memory refresh operation. By detecting redundancy test mode, the system configures the counter to operate only within the redundancy address space, effectively extracting the unnecessary normal area counting operations from the test sequence. This extraction eliminates wasted cycles while maintaining complete redundancy coverage.
3Loss of time
If the refresh counter is configured for redundancy area testing, then test time is reduced, but it cannot perform refresh operations for normal area
Solution Approach 1:
The refresh counter circuit is designed with multi-functionality to serve both redundancy testing and normal operation modes. By incorporating mode detection logic and configurable count limits, the same hardware circuit universally handles both scenarios - configuring itself for rapid redundancy testing when needed, and full-range refreshing during normal operation. This universality resolves the contradiction by making the system adaptable to different operational requirements.
Data Source
AI summary
Disclosed is a semiconductor storage device in which a cell array including a plurality of cells in need of refresh for data retention includes the redundancy area, which has a plurality of redundant cells for replacing faulty cells of a normal area within the cell array. When the redundancy area is tested, a refresh counter circuit for generating and outputting refresh addresses rearranges the address in such a manner that a row address of the redundancy area is substantially reduced and placed on a lower-order bit side inclusive of the LSB of the counter.