Combinatory Logic Decoding for Multi-Level Memory Cells
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Solution Overview
Problem
Existing memory devices face challenges in increasing bit density without significantly increasing the physical area of the memory die, particularly in volatile memory cells like DRAM, by storing more information in the same or smaller physical space.
Innovation Solution
Implementing a multilevel cell configuration that stores multiple non-zero voltage levels and uses both local and global sense amplifiers with varying numbers of latches, along with combinatory logic to decode information from memory cells, enhancing data storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel cell configuration is implemented to store multiple voltage levels, then storage capacity increases, but device complexity increases
Solution Approach 1:
The patent segments the reading process into multiple phases using local sense amplifiers that read voltage levels in sequence. Each local sense amplifier reads one voltage level at a time, and the results are combined by combinatory logic. This segmentation allows complex multilevel cells to be read using simpler, standardized reading circuits, thereby increasing storage capacity while controlling device complexity.
Solution Approach 2:
The patent introduces a temporal dimension to the reading process by using multiple read phases. Instead of reading all voltage levels simultaneously, the system reads them sequentially across different time phases using local sense amplifiers. This temporal multiplexing allows the system to achieve high storage capacity (1.5-2 bits per cell) without proportionally increasing the physical complexity of the memory array structure.
2Quantity of substance
If local and global sense amplifiers with varying numbers of latches are used, then bit density increases, but manufacturing complexity increases
Solution Approach 1:
The patent designs sense amplifiers with varying numbers of latches that can serve multiple functions. The same basic sense amplifier structure can be configured with different numbers of latches (e.g., 1 latch, 2 latches) to handle different reading scenarios. This multi-functionality allows the system to achieve high bit density through flexible configuration rather than requiring entirely different hardware for each case, thereby reducing manufacturing complexity.
Solution Approach 2:
The patent implements dynamic configuration of sense amplifiers where the number of active latches can be adjusted based on the specific reading operation. The system can dynamically activate different numbers of latches in the sense amplifiers depending on whether 1.5 bits or 2 bits need to be read from memory cells. This dynamic adaptability allows the system to optimize bit density without requiring separate dedicated circuits for each storage capacity scenario.
3Productivity
If combinatory logic is used to decode information from memory cells, then information retrieval efficiency improves, but circuit complexity increases
Solution Approach 1:
The patent introduces combinatory logic as an intermediary component between the local sense amplifiers and the final data output. The combinatory logic receives the partial readings from multiple local sense amplifiers and combines them to produce the complete decoded information. This intermediary layer efficiently processes and integrates the reading results, improving information retrieval efficiency while keeping the overall circuit complexity manageable through modular design.
Data Source
AI summary
A memory device includes first combinatory logic configured to receive multiple-digit representations of stored voltage values from each of N respective memory cells in a first memory array, and each of the memory cells is configured to store a charge having one of at least three different charge levels. The first combinatory logic can provide a first multiple-bit word, based on the received multiple-digit representations of the stored voltage values, and a number of bits in the first multiple-bit word is greater than N.