Shared-Selector Resistive Memory Assembly for Low-Leakage Density
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Solution Overview
Problem
Resistive memories face issues with leakage currents between memory cells in the same row or column, leading to degraded read and write capabilities, and existing solutions like using transistors as selectors increase the overall size of the memory chip.
Innovation Solution
An assembly of non-volatile resistive memories connected in parallel with a common selector layer, where each memory stack is oriented obliquely or perpendicularly to the selector electrode, sharing a common selector stack, reducing variability and maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If transistors are used as selectors to solve leakage current problems, then leakage current is reduced, but the overall size of the memory chip increases
Solution Approach 1:
The patent extracts the selection function from traditional transistor-based selectors and implements it through a dedicated selector layer integrated directly with the memory structure. This separation allows the selector to be optimized independently, achieving low leakage current without requiring large transistor structures, thus reducing overall chip size while maintaining effective leakage suppression.
Solution Approach 2:
The patent transitions from planar transistor-based selection to a vertical stacked architecture where the selector layer is positioned between memory cells in the vertical dimension. This dimensional change enables multiple memory cells to share common selector structures, reducing the area required per memory cell while maintaining effective leakage control through the selector's inherent properties.
2Productivity
If multiple memory cells share the same row or column, then memory density increases, but leakage current in non-selected cells degrades read/write capabilities
Solution Approach 1:
The patent introduces a selector layer as an intermediary component positioned between the word line and bit line connections and the memory cell. This selector acts as a gatekeeper that controls current flow, allowing high-density cell sharing while preventing leakage currents from degrading read/write operations by blocking current paths through non-selected cells.
3Device complexity
If a common selector layer is shared by multiple memory stacks, then device complexity is reduced, but variability in electrical characteristics increases
Solution Approach 1:
The patent applies local quality by creating laterally differentiated regions within the common selector layer. Each memory stack has its own laterally separated active region in the selector layer, allowing the common structure to serve multiple cells while maintaining independent electrical characteristics for each stack, thus reducing variability despite sharing the same selector layer.
Data Source
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AI summary
The invention relates to an assembly (1a) of non-volatile resistive memories associated with a selector, comprising: - a selector layer (11) and an upper electrode (12); - a first memory stack (20) comprising a first active layer (21), extending against a part of a lateral surface (121) of the upper electrode (12); - a second memory stack (30) comprising a second active layer (31), extending against another part of the lateral surface (122) of the upper electrode (12); the upper electrode (12) being common to the first and the second memory stack (20, 30).