Semiconductor Memory Pulse Width Control
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Solution Overview
Problem
Semiconductor memory devices face compatibility issues with operational frequencies due to fixed pulse widths in column selection signals, which are sensitive to process, voltage, and temperature variations, leading to degraded operational characteristics and limited frequency compatibility.
Innovation Solution
A semiconductor memory device design that includes a reset signal generating unit, a pulse width determination unit, and an address decoding unit, which generate a column selection signal with a pulse width adjusted according to the operational frequency, using a clock signal to ensure stability and compatibility across varying frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed pulse width is used for the column selection signal, then the circuit design is simple, but the operational characteristics are degraded and frequency compatibility is limited due to sensitivity to process, voltage, and temperature variations
Solution Approach 1:
The patent applies dynamics by making the pulse width of the column selection signal adjustable rather than fixed. A control signal generation unit dynamically adjusts the pulse width based on detected operational frequency, allowing the system to adapt to different operating conditions and maintain reliable operation across varying frequencies while avoiding the sensitivity issues of fixed pulse width designs to process, voltage, and temperature variations
Solution Approach 2:
The patent changes the parameter of pulse width from a fixed value to a dynamically adjustable parameter. By modifying the pulse width based on operational frequency detection, the system optimizes its performance for different frequency ranges, resolving the contradiction between design simplicity and operational reliability
2Device complexity
If a fixed pulse width is used for the column selection signal, then the circuit implementation is straightforward, but compatibility with varying operational frequencies is poor
Solution Approach 1:
The system becomes dynamic by detecting the operational frequency and adjusting the column selection signal pulse width accordingly. This allows the circuit to be compatible with multiple operational frequencies while maintaining a relatively simple overall structure through the use of standard delay circuits and control logic
Solution Approach 2:
The patent achieves universality by enabling the memory device to operate reliably across multiple frequency ranges. The control signal generation unit provides multi-functionality by adapting the pulse width to match different operational frequencies, making the device versatile and frequency-compatible
3Reliability
If conventional delaying circuits are used to adjust pulse width, then the operational characteristics can be optimized, but the layout burden increases
Solution Approach 1:
The patent optimizes the pulse width parameter by using a controlled number of delay circuits rather than extensive conventional delaying circuits. This reduces the layout area while still achieving the necessary pulse width adjustment for operational characteristics optimization
Solution Approach 2:
The patent applies partial action by using a limited number of delay circuits (first, second, and third delay circuits) rather than comprehensive delaying networks. This partial implementation is sufficient to achieve the required pulse width control and operational optimization without the excessive layout burden of more extensive circuits
Data Source
AI summary
A semiconductor memory device includes a reset signal generating unit configured to generate a reset control signal by delaying a column command signal by an amount of time varying proportional to an operational frequency. A pulse width determination unit is configured to determine a pulse width of a column selection signal in response to the column command signal and the reset control signal. An address decoding unit is configured to generate the column selection signal corresponding to a corresponding column address in response to an output signal of the pulse width determination unit.