Memory Read Timing Control for Lower Precharge Power
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Solution Overview
Problem
Existing memory storage devices waste power consumption due to uniform read durations set for all memory cells, regardless of their proximity to the sensing amplifier, leading to unnecessary power consumption during precharge operations.
Innovation Solution
A memory storage device with a controller circuit that adjusts the read period duration based on the detection result from a sensing amplifier device, allowing shorter read periods for nearer memory cells to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform read duration is set for all memory cells, then all memory cells can be read reliably, but power consumption increases due to unnecessary precharge operations for nearer memory cells
Solution Approach 1:
The patent applies local quality by differentiating read operations based on the spatial location of memory cells. Nearer memory cells use a first read duration while farther memory cells use a second read duration, optimizing power consumption for each location rather than applying a uniform duration across all cells.
Solution Approach 2:
The patent implements dynamics by making the read duration adjustable based on memory cell location. The system dynamically selects between first and second read durations according to whether the target memory cell is nearer or farther from the sensing amplifier, allowing adaptive optimization of power consumption.
2Ease of operation
If longer read duration is used for nearer memory cells, then reading is simplified, but power consumption increases due to extended precharge operations
Solution Approach 1:
The patent applies local quality by differentiating read operations based on the spatial location of memory cells. Nearer memory cells use a first read duration while farther memory cells use a second read duration, optimizing power consumption for each location rather than applying a uniform duration across all cells.
Solution Approach 2:
The patent applies partial action by using a shorter first read duration for nearer memory cells that requires less sensing time, rather than applying the longer second read duration to all cells. This partial approach reduces unnecessary power consumption while maintaining sufficient read capability for nearer cells.
3Loss of energy
If shorter read duration is used for nearer memory cells, then power consumption is reduced, but reading reliability may be compromised
Solution Approach 1:
The patent applies local quality by differentiating read operations based on the spatial location of memory cells. Nearer memory cells use a first read duration while farther memory cells use a second read duration, optimizing power consumption for each location rather than applying a uniform duration across all cells.
Solution Approach 2:
The patent implements feedback by using detection results from the sensing amplifier to determine whether to extend the read duration. When the sensing amplifier detects that a sufficient voltage difference has been achieved, it signals the controller to end the read operation early, ensuring reliability while minimizing power consumption.
4Measurement precision
If read duration is extended for all memory cells, then reading accuracy is improved, but precharge operations consume unnecessary power
Solution Approach 1:
The patent applies local quality by differentiating read operations based on the spatial location of memory cells. Nearer memory cells use a first read duration while farther memory cells use a second read duration, optimizing power consumption for each location rather than applying a uniform duration across all cells.
Solution Approach 2:
The patent implements feedback by using detection results from the sensing amplifier to determine whether to extend the read duration. When the sensing amplifier detects that a sufficient voltage difference has been achieved, it signals the controller to end the read operation early, ensuring reliability while minimizing power consumption.
Data Source
AI summary
Provided is a memory storage device including a memory cell array, a sensing amplifier device, and a controller circuit. The memory cell array includes a plurality of memory cells. The sensing amplifier device is coupled to at least one memory cell of the plurality of memory cells via a bit line and a complementary bit line. The sensing amplifier device detects differential pair signals on the bit line and the complementary bit line and outputs a detection result. The controller circuit is coupled to the sensing amplifier device. The controller circuit is configured to adjust a duration of a read period of the at least one memory cell according to the detection result.