MRAM Read Circuit Using Source-Line Bias to Cut Leakage
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Solution Overview
Problem
Conventional magneto resistive memory devices suffer from low reliability and high power consumption due to high leakage currents and low Ion/Ioff ratios, making it difficult to discriminate the state of a selected memory cell amidst unselected cells, especially at higher temperatures.
Innovation Solution
A method and device architecture that applies a first voltage greater than ground on the bit line and a second voltage greater than the first on the source line, using NMOS transistors with body effect to increase the threshold voltage, reducing leakage currents and enhancing the Ion/Ioff ratio, and includes a sense amplifier to detect the read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reading methods are used with standard voltage application, then the memory device can operate with simple control circuitry, but high leakage currents occur and the Ion/Ioff ratio remains low, making it difficult to discriminate selected cell states
Solution Approach 1:
The patent applies parameter changes by reversing the conventional voltage application method: instead of applying voltage to the bit line and grounding the source line, the patent applies a first voltage (e.g., 0V or ground) to the bit line and a second voltage (e.g., read voltage) to the source line. This parameter reversal changes the operating conditions of the selection transistor, causing leakage current to flow from the source line to the bit line rather than from the bit line to the source line, thereby improving the Ion/Ioff ratio and enabling better discrimination of selected cell states.
2Reliability
If standard selection transistor configuration is used, then the device architecture remains simple, but power consumption increases due to high leakage currents from unselected cells
Solution Approach 1:
The patent changes the voltage parameters applied to the source line and bit line. By applying a higher voltage to the source line compared to the bit line, the selection transistor's threshold voltage is effectively increased due to the body effect, which suppresses leakage current from unselected cells. This parameter change reduces power consumption while maintaining read operation reliability.
3Measurement precision
If conventional voltage polarity is applied during read operations, then the control circuitry remains straightforward, but the Ion/Ioff ratio is insufficient to reliably detect memory cell states
Solution Approach 1:
The patent applies inversion by reversing the conventional voltage polarity and application points. Instead of applying read voltage to the bit line and grounding the source line, the patent applies read voltage to the source line and grounds (or applies lower voltage) to the bit line. This inversion causes the selection transistor to conduct leakage current in the opposite direction, improving the Ion/Ioff ratio and enabling reliable memory cell state detection without significantly increasing control circuitry complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces leakage currents, improving the Ion/Ioff ratio by 2000 times, enhancing reliability and reducing power consumption, allowing for better discrimination of the selected cell state.
Implementation Method 1
The resistance value between the pinned layer 2c and the free layer 2b is dependent on the actual state of the free layer magnetization orientation. When the free layer 2b and the pinned layer 2c have parallel magnetizations, the magnetic tunnel junction presents a relatively lower electric resistance, whereas in the antiparallel magnetizations the magnetic tunnel junction presents a relatively higher electric resistance.
Implementation Method 2
A method and device architecture that applies a first voltage greater than ground on the bit line and a second voltage greater than the first on the source line, using NMOS transistors with body effect to increase the threshold voltage, reducing leakage currents
Data Source
Figure 1a~2
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Figure 5~6
AI summary
The invention relates to a magneto resistive memory de device (100) comprising a memory array (10) comprising at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB) being associated with a plurality of memory cells (1) each presenting a magnetic tunnel junction (2) and each presenting at least one selection transistor (RT) to selectively connect the bit line (BL). The memory array also comprises a peripheral block configured to apply a first voltage (Vread) greater than ground voltage (Vss) on the bit line (BL) and applying a second voltage (VSL) greater than the first voltage (Vread) on the at least one source line (SL, SLB). The state stored in the selected cell (1) is detected by using a sense amplifier (SA) of the peripheral block associated with the at least one bit line (BL) to sense the current flowing in the bit line (BL).