Vertical SRAM Cell Layout Using Double-Sided Routing to Cut RC Delay
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Solution Overview
Problem
Existing SRAM designs face challenges in scaling down to advanced IC technology nodes due to increased resistance and capacitance in multilayer interconnects, which hinder signal routing efficiency and memory performance.
Innovation Solution
A 4CPP-1OD SRAM cell layout is proposed, featuring a vertical stacking of transistors and a double-sided routing structure, reducing SRAM cell area, density, and interconnect resistance/capacitance by using a four times contacted poly pitch layout with double-sided multilayer interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is shrunk to increase functional density, then production efficiency and cost are improved, but resistance and capacitance of interconnects increase causing signal delays
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional vertical routing through stacked transistor configurations. This dimensional change allows interconnects to route signals vertically through multiple layers, reducing the horizontal distance and number of interconnect segments required, thereby decreasing resistance and capacitance while maintaining compact footprint for high functional density
2Reliability
If interconnect width is increased to reduce resistance, then signal routing performance is improved, but device area increases
Solution Approach 1:
The invention utilizes vertical stacking to route interconnects through the z-dimension, allowing signals to travel shorter horizontal distances with narrower widths while achieving the same or better signal routing performance. The vertical architecture enables compact interconnect paths that reduce both resistance and area occupation simultaneously
3Productivity
If multilayer interconnect complexity is increased to achieve compact routing, then functional density is improved, but resistance and capacitance increase causing signal delays
Solution Approach 1:
The patent segments the interconnect routing into distinct vertical layers, with each layer handling specific signal paths. This segmentation allows for optimized routing in each layer, reducing the total interconnect length and minimizing resistance and capacitance effects while achieving high functional density through efficient three-dimensional space utilization
Data Source
AI summary
A four times contacted poly pitch (4CPP) static random-access memory (SRAM) cell layout is disclosed that forms six SRAM transistors from one OD region and four poly lines at a frontside of a substrate and provides a double-sided routing structure for word lines, bit lines, and/or voltage lines. For example, a vertical SRAM is disclosed that stacks transistors, vertically, to facilitate scaling needed for advanced IC technology nodes and improve memory performance. The vertical SRAM further includes a double-sided routing structure, which facilitates placement of bit lines, word lines, and voltage lines in a backside metal one (M1) layer and/or a frontside M1 layer to minimize line capacitance and line resistance.