Semiconductor Division Strobe Signal Generation Circuit
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Solution Overview
Problem
High-performance semiconductor memory devices require improved integration density and operation speed, which existing SDR synchronous semiconductor memory devices cannot meet, necessitating the development of DDR synchronous semiconductor memory devices that operate at higher speeds without increasing external clock signal frequency.
Innovation Solution
The semiconductor device generates a division strobe signal by dividing a data strobe signal using a division period signal generation circuit and clock sampling circuit, enabling synchronization with a write period set by a write command and latency information, and sequentially generating division strobe signals to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DDR synchronous semiconductor memory devices are used to operate at higher speeds, then operation speed is improved, but device complexity increases due to the need for division strobe signal generation circuits
Solution Approach 1:
The patent divides the data strobe signal into multiple division strobe signals (first division strobe signal, second division strobe signal, etc.) using division period signal generation circuits. This segmentation allows the memory device to perform multiple operations within a single clock cycle, achieving higher operation speed while managing complexity through systematic signal division
Solution Approach 2:
The patent employs dynamic control of the division period signal generation circuits to generate division strobe signals at different phases. The circuits dynamically adjust the timing and phase of division strobe signals based on clock cycles, enabling flexible operation at higher speeds without fixed complex hardware structures
2Reliability
If the division period signal is disabled early to prevent malfunction, then reliability is improved, but the sampling period cannot be extended to accommodate longer write periods
Solution Approach 1:
The patent applies preliminary action by disabling the division period signal generation circuits before the sampling period ends. The division period signal is disabled in advance based on predicted timing, allowing the sampling circuit to complete its longer sampling period without generating erroneous division strobe signals, thus preventing malfunction while accommodating extended write periods
3Adaptability or versatility
If the sampling period is extended to match longer write periods, then adaptability is improved, but the risk of malfunction increases due to delayed division period signal disablement
Solution Approach 1:
The patent implements feedback control where the division period signal generation circuits continuously monitor the sampling period status and adjust their operation accordingly. The circuits receive feedback about the extended sampling period and dynamically adjust the timing of division strobe signal generation to ensure they are disabled at the appropriate moment, preventing malfunction while maintaining adaptability to longer write periods
Data Source
AI summary
A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.