Asymmetric Column Select Transistor for DRAM Bit Line Disturbance
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Solution Overview
Problem
The operation characteristics of semiconductor memory devices, particularly dynamic random access memory (DRAM), are affected by the column select transistor, where increasing the capacity of the transistor to improve writing characteristics often deteriorates reading characteristics due to increased operation current, leading to bit line disturbance and insufficient margin for preventing errors.
Innovation Solution
A semiconductor memory device is designed with a column select transistor having asymmetrical source/drain resistances, where a first source/drain with lower resistance functions as the source during writing and the second source/drain with higher resistance functions as the drain, and vice versa during reading, to manage current flow and prevent bit line disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacity of the column select transistor is increased to improve writing characteristics, then writing performance is improved, but reading characteristics deteriorate due to increased operation current causing bit line disturbance
Solution Approach 1:
The patent applies asymmetry by configuring the column select transistor with different resistance values for its two source/drain regions. Specifically, the first source/drain region has a first resistance value while the second source/drain region has a second resistance value that is higher than the first. This asymmetric resistance configuration allows the transistor to exhibit different current characteristics during writing versus reading operations, thereby improving writing performance while controlling reading current to prevent bit line disturbance
Solution Approach 2:
The patent implements local quality by creating non-uniform electrical properties within the transistor structure. The first source/drain region is doped with a first dopant concentration while the second source/drain region is doped with a second dopant concentration that is lower than the first. This localized variation in dopant concentration creates the desired resistance asymmetry, allowing different parts of the transistor to serve different functional requirements for writing and reading operations
2Speed
If the operation current of the column select transistor is increased to improve writing characteristics, then writing speed is improved, but bit line disturbance increases reducing the margin for preventing errors
Solution Approach 1:
The asymmetric resistance configuration enables the transistor to provide high current during writing operations (when the low-resistance source/drain is active) while limiting current during reading operations (when the high-resistance source/drain is active). This resolves the contradiction by allowing fast writing speeds while preventing bit line disturbance during reading
Solution Approach 2:
The patent changes the electrical parameters of the transistor by implementing different dopant concentrations in the two source/drain regions. This parameter variation creates the resistance asymmetry that allows the transistor to dynamically adjust its current-carrying capacity based on the operation mode, achieving high writing speed while maintaining low reading current to avoid bit line disturbance
Data Source
AI summary
A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain.