Shared Pass Transistor Memory Circuit for Compact Layout
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Solution Overview
Problem
The challenge of reducing the size of memory circuits is hindered by transistor matching issues during miniaturization, necessitating a layout optimization rather than a reduction in transistor count.
Innovation Solution
A memory circuit design incorporating an amplifier with specific transistor configurations and pass transistors that are controlled by control signals during read/write and idle stages, allowing for reduced transistor count and optimized layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the manufacturing process is miniaturized to reduce chip size, then the overall chip area is reduced, but transistor matching problems become more serious
Solution Approach 1:
The patent combines the functions of the first pass transistor and second pass transistor into a single shared transistor. This shared pass transistor is controlled by control signals to perform both column selection operations and precharge operations, thereby reducing the total transistor count and enabling chip size reduction while maintaining functional reliability through proper signal timing control
2Area of stationary object
If the quantity of transistors is reduced to optimize layout, then chip area is reduced, but transistor matching problems worsen
Solution Approach 1:
The shared pass transistor is designed to perform multiple functions: it acts as a column selection transistor during read/write operations when activated by column selection signals, and serves as a precharge transistor during idle stages when activated by precharge signals. This multi-functional design reduces the total transistor quantity while maintaining manufacturing precision through unified transistor design
Data Source
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AI summary
The present disclosure provides a memory circuit, which may at least include: an amplifier, the amplifier having a first node and a second node, the first node being electrically connected to a first data line, the second node being electrically connected to a first reference data line, and the amplifier being configured to amplify a voltage difference between the first data line and the first reference data line; and a first pass transistor, the first pass transistor being electrically connected to the first node and a second data line, and the first pass transistor being configured to be turned on based on a control signal in at least a part of a time period at a read/write stage, and be turned on based on the control signal in at least a part of a time period at an idle stage.