Asymmetric Bit Line Contact Spacers for Dense Memory Arrays
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by the techniques used for forming fine patterns, which require expensive apparatuses and hinder further increases in density and current driving capability.
Innovation Solution
A semiconductor memory device design featuring a semiconductor substrate with defined active portions, bit line structures, conductive pads, and spacers, where the conductive pads have flat bottom surfaces and varying widths, and bit line contact spacers with different widths, enhancing the integration density and current driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fine pattern formation techniques are used to increase integration density, then integration density improves, but manufacturing cost increases due to expensive apparatus requirements
Solution Approach 1:
The patent transitions from two-dimensional planar device structures to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked above the substrate, with bit lines extending vertically through the stack to connect to memory cells in different layers. This vertical stacking enables significantly higher integration density without requiring proportionally smaller lateral feature sizes, thereby avoiding the need for extremely expensive fine pattern formation apparatus.
2Ease of manufacture
If conventional 2D semiconductor device structures are used, then manufacturing is simpler, but current driving capability is limited
Solution Approach 1:
The memory device is segmented into multiple stacked layers, each containing memory cells that can be independently accessed. The bit line structure is segmented to extend vertically through the stack, with different portions connecting to memory cells in different layers. This segmentation allows multiple memory cells to be connected in parallel through the same bit line, thereby enhancing current driving capability while maintaining manufacturing simplicity through modular layer-by-layer fabrication.
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.