Asymmetric Memory Array Layout for Balanced RC Delays
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Solution Overview
Problem
Integrated circuits experience unbalanced signal propagation speeds and active powers due to unequal RC loads on complementary data lines caused by uneven distribution of memory cells, leading to inconsistent access speeds and power consumption during read/write operations.
Innovation Solution
Asymmetric arrangement of memory cells and complementary data lines, where one segment has fewer memory cells with shorter data lines and another segment has more memory cells with longer data lines, balancing the RC loads and reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are evenly distributed across segments, then manufacturing simplicity is maintained, but signal propagation speed becomes unbalanced and access speed consistency deteriorates
Solution Approach 1:
The patent applies asymmetry by intentionally creating unequal distributions of memory cells across different segments. Specifically, a first segment contains a first number of memory cells while a second segment contains a second number of memory cells, where the first number differs from the second number. This asymmetric arrangement compensates for differences in data line lengths, balancing RC loads and achieving consistent signal propagation speeds across all data lines despite the unequal memory cell distribution.
Solution Approach 2:
The patent implements local quality by tailoring the memory cell arrangement to specific segment characteristics. Each segment is configured with a specific number of memory cells based on its position and data line length requirements. The first segment has a different memory cell density compared to the second segment, optimizing each local region's contribution to overall signal balance rather than applying a uniform distribution across the entire device.
2Quantity of substance
If data lines are made longer to access more memory cells, then storage capacity increases, but RC load increases causing signal delay and power consumption to worsen
Solution Approach 1:
The patent uses asymmetry to balance RC loads by creating segments with different numbers of memory cells and different data line lengths. The first segment has a first number of memory cells with corresponding first data lines, while the second segment has a second number of memory cells with second data lines. The asymmetric arrangement ensures that despite varying data line lengths, the RC loads are balanced, preventing excessive signal delay even as storage capacity increases.
Solution Approach 2:
The patent divides the memory array into multiple segments (first segment and second segment), each with its own set of data lines and memory cells. This segmentation allows independent optimization of each segment's characteristics, enabling the system to accommodate longer data lines in certain segments while maintaining overall signal integrity through balanced RC loads across all segments.
3Speed
If data lines are made shorter to reduce RC load, then signal propagation speed improves, but the number of accessible memory cells decreases
Solution Approach 1:
The patent applies asymmetry by configuring different segments with different numbers of memory cells and different data line lengths. The first segment contains a first number of memory cells accessible via first data lines, while the second segment contains a second number of memory cells accessible via second data lines. This asymmetric design allows the system to maintain fast access speeds in segments with shorter data lines while still providing total storage capacity across all segments, as each segment's characteristics are optimized for its specific role.
Data Source
AI summary
A method includes: turning on a first switch coupled between a first array of memory and a voltage supply according to a first charge signal; turning on a second switch coupled between a second array of memory and the voltage supply according to a second charge signal different from the first charge signal; and generating the first charge signal and the second charge signal according to a word line address. The second array of memory is located between the second switch and the first array of memory.