Out-of-Order Data Buffer with Validity Detection Circuit
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Solution Overview
Problem
In Systems-on-Chip (SoCs) and Systems-in-Package (SiPs), out-of-order data transmission due to shared communication channels like Network-On-Chip (NoC) leads to unordered data packets, requiring mechanisms to determine when all data have been received without introducing significant latency or increasing clock frequency complexity.
Innovation Solution
A buffer with a detection circuit that generates validity signals for memory locations, using a search pointer to identify the last memory location with valid data, allowing for early determination of data completeness and enabling early allocation of memory resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a sequential detection method is used to determine data completeness, then the circuit complexity is reduced, but the latency increases significantly
Solution Approach 1:
The buffer memory is segmented into multiple regions, each with its own validity detection mechanism. The detection circuit is divided into multiple independent units that can simultaneously check different segments, enabling parallel validation while keeping each individual detection unit simple in structure
Solution Approach 2:
Instead of sequentially checking all memory locations, the system performs partial parallel checks on multiple regions simultaneously. The detection circuit uses multiple validity registers and comparison units that operate in parallel to determine data completeness faster than a purely sequential approach would require
2Loss of time
If a parallel detection approach is used to determine data completeness, then the latency is reduced, but the clock frequency complexity increases
Solution Approach 1:
The parallel detection circuit is segmented into multiple independent validation units, each handling a specific memory region. This segmentation allows the system to achieve parallel detection speed without requiring a single complex high-frequency clock, as each segment can operate independently at lower frequencies
Solution Approach 2:
The patent introduces a spatial dimension to the detection process by organizing validity information across multiple parallel registers and memory regions. Instead of increasing clock frequency in a single dimension, the system distributes the detection workload across multiple spatial dimensions (parallel detection units), achieving speedup without frequency complexity
3Device complexity
If memory locations are not validated early, then the buffer structure remains simple, but memory allocation efficiency decreases
Solution Approach 1:
The detection circuit performs preliminary validation of memory locations as data is being written, before the buffer needs to be allocated or processed further. Validity bits are set in advance during the write operation, enabling early determination of data completeness and facilitating faster subsequent memory management operations
Solution Approach 2:
The detection circuit provides continuous feedback about the validity status of memory locations. This feedback mechanism allows the buffer management system to make informed decisions about memory allocation and data processing without waiting for complete sequential validation, thereby improving overall memory allocation efficiency
Data Source
AI summary
A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.