Command-Based tWR Precharge Control for SDRAM
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Solution Overview
Problem
Conventional SDRAM memory arrays require complex and resource-intensive tWR precharge circuits to ensure data integrity, which increases logic requirements and power consumption, especially as memory chips shrink in size.
Innovation Solution
A command-based tWR precharge circuit is introduced, featuring a synchronous path for Write-with-Autoprecharge signals and an asynchronous path for bank address signals, allowing for reduced logic and eliminating the need for clock-loading registers, thereby simplifying the precharge timing mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional tWR precharge circuits are used to ensure data integrity, then data storage reliability is improved, but logic complexity and power consumption increase
Solution Approach 1:
The precharge control is segmented by bank, with each bank having its own independent precharge control logic. This allows the system to track write operations and precharge only the specific banks that require it, rather than using complex global control logic that monitors all banks simultaneously.
Solution Approach 2:
The patent extracts the tWR timing control logic from the main control path and implements it as separate bank-level counters and control signals. This separation simplifies the main control logic while ensuring data integrity through dedicated bank-specific timing control.
2Reliability
If conventional tWR precharge circuits are used to ensure data integrity, then data storage reliability is improved, but power consumption increases
Solution Approach 1:
Power consumption is reduced by segmenting the precharge control to operate independently in each bank. Only the banks that have active write operations require precharge control, allowing other banks to remain in low-power states without complex global coordination.
Solution Approach 2:
Each bank's precharge control operates autonomously using local counters and signals to track write operations and trigger precharge when needed. This self-service approach eliminates the need for power-intensive centralized control logic while maintaining data integrity.
3Area of stationary object
If memory chips are reduced in size, then chip area is reduced, but logic circuitry density and power consumption become more critical
Solution Approach 1:
The memory array is divided into multiple independent banks, each with simplified precharge control logic. This segmentation allows compact layout while reducing the complexity of control circuitry, as each bank operates independently with its own simple counter and control signals rather than requiring complex global control.
Solution Approach 2:
Write address buffers and bank counters are prepared in advance to track write operations before precharge is needed. This preliminary tracking allows the simplified control logic to determine when precharge is required without complex real-time analysis, reducing logic density requirements.
Data Source
AI summary
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and various bank address signals are provided to the asynchronous path. In another embodiment, the initiation of the bank address signals may be provided asynchronously to the assertion of the Write-with-Autoprecharge signal.