Memory Bank Fine-Grained Refresh for Higher I/O Availability
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Solution Overview
Problem
Volatile memory devices face performance limitations due to increasing refresh operation times as they transition to higher integration, capacity, and speed, necessitating a more efficient refresh strategy.
Innovation Solution
Implementing fine-grained refresh operations, which involve a memory device with a control logic circuit that manages refresh operations based on a refresh target determination list and pointer value, allowing for a combination of regular and fine-grained refresh commands to optimize refresh efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If regular refresh operations are performed to maintain data integrity in volatile memory devices, then reliability is improved, but productivity deteriorates due to increased refresh time consuming a larger portion of total operating time
Solution Approach 1:
The patent divides the memory bank into multiple memory cell arrays (first plurality and second plurality) and implements separate refresh operations for each array. The control logic circuit performs a first refresh operation on the first plurality of memory cell arrays and a second refresh operation on the second plurality of memory cell arrays, allowing overlapping execution of refresh and I/O operations on different arrays, thus reducing the impact of refresh on overall productivity while maintaining data integrity across all arrays
Solution Approach 2:
The patent enables dynamic switching between regular refresh mode and fine-grained refresh mode based on operational requirements. The control logic circuit can selectively execute fine-grained refresh operations on specific memory cell arrays when I/O operations are being performed on other arrays, dynamically adjusting the refresh strategy to balance reliability and productivity based on real-time operational context
2Productivity
If higher integration, capacity, and input/output speeds are implemented in volatile memory devices, then productivity is improved, but the ratio of operating time spent on refresh operations increases, worsening productivity
Solution Approach 1:
The patent segments the memory bank into multiple independent memory cell arrays that can be refreshed independently. This allows the control logic circuit to perform fine-grained refresh operations on specific arrays without halting I/O operations on other arrays, thereby reducing the time loss associated with refresh operations while maintaining the high integration and capacity benefits
Solution Approach 2:
The control logic circuit performs fine-grained refresh operations in advance or during periods when I/O operations are not required on specific memory cell arrays. By proactively refreshing memory cell arrays before they are needed for I/O operations, the patent reduces the time loss ratio while maintaining the high input/output speeds required for modern applications
Data Source
AI summary
According to embodiments of the present disclosure, an operation method of a memory device including a memory bank, which includes a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays may be provided. The operation method may comprise receiving a fine-grained refresh command, identifying a refresh target pointer value for a refresh target determination list, which includes a plurality of row addresses for the memory bank, identifying a pointed row address corresponding to the refresh target pointer value, among the plurality of row addresses, determining a first memory cell array type corresponding to the pointed row address, and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.