Vertical Memory Transistor Structure With Segmented Bit Line Contact
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased fabrication complexity and cost as feature sizes approach a lower limit, limiting memory density and efficiency.
Innovation Solution
Implementing vertical transistors with a semiconductor body extending in a first direction, where the bit line is separated from the channel portion by a second terminal, allowing for a staggered layout and multiple stacked storage units, reducing area occupation and simplifying interconnect structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to vertical (3D) transistor structure, where the semiconductor body extends in the vertical direction perpendicular to the substrate. This dimensional change allows memory cells to be stacked vertically, increasing memory density without proportionally increasing fabrication complexity, as the vertical stacking can be achieved through sequential deposition and etching processes
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but fabrication cost increases
Solution Approach 1:
By adopting vertical transistors with semiconductor bodies extending perpendicular to the substrate, the patent enables higher memory density through 3D stacking. This approach can reduce fabrication cost per bit compared to continued planar scaling, as the vertical structure can be formed using standard deposition and etching techniques applied in sequential layers, potentially reducing the number of lithography steps required
3Area of moving object
If vertical transistors are implemented with bit line separated from channel portion by second terminal, then area occupation is reduced, but device structure complexity increases
Solution Approach 1:
The patent segments the bit line connection by introducing a second terminal that separates the bit line from the channel portion of the semiconductor body. This segmentation allows the bit line to contact only the source or drain region, reducing the overlapping area between bit line and channel. The segmented structure enables more compact cell layout while managing complexity through modular connection design
Solution Approach 2:
The vertical transistor structure with segmented bit line connection utilizes the vertical dimension to separate functional regions. The semiconductor body extends vertically, allowing the bit line to access the source/drain at a different vertical level than the channel, thereby reducing planar area occupation while organizing complexity in the vertical dimension rather than increasing it in the planar dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell density, reduces fabrication complexity, and improves yield by minimizing the area occupied by transistors and simplifying the layout of interconnect structures, while suppressing the floating body effect through partial doping.
Implementation Method 1
The semiconductor body includes a doped source, a doped drain, and a channel portion
Data Source
AI summary
In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.