Phased Per-Read Memory Controller for Parallel Flash Reads

The memory controller is segmented into multiple independent per-read memory controllers, each capable of handling individual read commands. This segmentation allows the system to process multiple reads in parallel while enabling selective activation of only the necessary controller instances, thereby improving throughput without proportionally increasing power consumption across the entire controller block.

The system dynamically selects and activates a specific number of per-read memory controller instances based on the current read workload. When fewer parallel reads are needed, fewer controller instances are activated, reducing power consumption. When higher throughput is required, more instances are activated. This dynamic adaptation resolves the contradiction between maintaining high productivity capability and reducing actual power usage during light workloads.

By dividing the memory controller into multiple identical, independent per-read controller instances, the complex control logic is segmented and distributed across instances rather than concentrated in a single complex controller. Each instance handles its own read command independently, simplifying the control logic within each unit while enabling parallel processing capability at the system level.

The patent creates multiple copies of a standardized per-read memory controller template. Instead of designing one complex controller that must manage all parallel operations, the system uses several identical, simpler controller copies that can be selectively activated. This copying approach reduces the complexity of individual control units while achieving the desired parallel processing throughput.