Multi-Bit Memory Cell Layout to Prevent Half-Selected Writes
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Solution Overview
Problem
Volatile memory devices, such as SRAM, suffer from a half-selected problem during write operations, leading to data flip and increased current consumption due to unselected bit cells affecting stored data.
Innovation Solution
A memory device with a multi-bit cell structure that includes a plurality of bit cells connected to shared write and read word lines, along with input and read circuits, uses transfer gates and latches to control data input and output, minimizing the number of CMOS devices and preventing data collisions during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional SRAM cell structure with shared word lines is used, then the area usage is reduced, but data flip occurs during write operations due to half-selected bit cells affecting stored data
Solution Approach 1:
The patent divides the write operation control into two independent parts: column selection lines that select specific bit cells, and write word lines that enable write mode. This segmentation allows only the selected bit cells to be affected by write operations, preventing half-selected bit cells from causing data flip while maintaining area efficiency through shared word lines.
Solution Approach 2:
The patent introduces column selection lines as an intermediary control mechanism between the write data and the bit cells. These column selection lines act as a gate that determines which bit cells receive write data, preventing unselected bit cells from being affected by write operations and thus eliminating the data flip problem.
2Device complexity
If conventional SRAM write operations are performed with shared word lines, then the circuit complexity is reduced, but current consumption increases due to half-selected bit cells affecting stored data
Solution Approach 1:
The patent segments the word line functionality into read word lines and write word lines, with separate column selection lines controlling write operations. This segmentation ensures that only selected bit cells undergo write operations, minimizing current consumption by preventing half-selected bit cells from being affected, while keeping the overall circuit structure relatively simple.
Solution Approach 2:
The patent employs dynamic control of transfer gates within bit cells that are conditionally activated based on column selection and write word line signals. This dynamic activation ensures that only selected bit cells consume write current, reducing overall current consumption while maintaining simple circuit architecture through conditional gate activation.
3Manufacturing precision
If multiple bit cells share common write word lines, then the manufacturing precision requirements are reduced, but data collisions occur during write operations
Solution Approach 1:
The patent segments the control signals for write operations into column selection lines that identify specific bit cells and write word lines that enable write mode. This segmentation ensures that write data is directed only to intended target bit cells, preventing data collisions even when multiple bit cells share common write word lines, while maintaining relaxed manufacturing precision requirements.
Data Source
AI summary
A memory device includes a plurality of multi-bit cells, wherein each of the plurality of multi-bit cells includes a plurality of bit cells commonly connected to a column selection line, respectively connected to a plurality of write word lines, and respectively connected to a plurality of read word lines and an input circuit configured to provide a first signal corresponding to a bit to be written, to the plurality of bit cells, wherein each of the plurality of bit cells includes a latch circuit configured to receive the first signal in response to a write word line being activated and latch the first signal in response to the write word line being deactivated or a column selection line being deactivated, and a read circuit configured to output the first signal stored in the latch circuit to a bit line in response to a read word line being activated.