Ferroelectric Memory Voltage Control for Lower Refresh Interference
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Solution Overview
Problem
Conventional ferroelectric memories face high refresh frequencies due to interference voltages affecting unselected memory cells, leading to reduced implementability and performance.
Innovation Solution
A control method and apparatus that reduces interference voltages by applying specific voltage differences between unselected memory cells during active phases, maintaining an information read window and minimizing refresh frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional voltage control is used during active phase, then memory access operation is performed, but interference voltage causes high refresh frequency
Solution Approach 1:
The active phase is divided into two sub-phases: first sub-phase where unselected transistors are conducted with reduced voltage difference, and second sub-phase where selected transistor is conducted with full voltage difference. This segmentation allows different voltage control strategies for different operational stages, reducing interference while maintaining access functionality.
Solution Approach 2:
Different voltage control strategies are applied to different memory cells based on their selection state. Unselected memory cells receive reduced voltage difference (1/3 Vw) to minimize interference, while the selected memory cell receives full voltage difference (Vw) to ensure proper read/write operation. This local differentiation reduces overall interference without compromising access performance.
2Reliability
If voltage difference is increased for unselected memory cells, then read/write interference resistance improves, but information read window size reduces
Solution Approach 1:
The voltage difference parameter is dynamically adjusted based on memory cell selection state. Unselected cells use reduced voltage difference (1/3 Vw) to maintain interference resistance, while the selected cell uses full voltage difference (Vw) to preserve the information read window. This parameter change strategy optimizes both interference resistance and read window size simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances ferroelectric memory performance by reducing refresh frequency and increasing resistance to read/write interference, thereby improving implementability.
Implementation Method 1
the change of the charge on the BL is mainly caused by a polarization charge released by a ferroelectric capacitor due to polarity switching when the ferroelectric capacitor of the memory cell is under an action of a voltage that exceeds a coercive field voltage Vc
Data Source
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AI summary
Embodiments of this application provide a control method and apparatus for a memory, and an electronic device, and relate to the field of storage technologies. The memory includes a plurality of transistors and a memory cell array. Memory cells located in a same column are coupled to a same transistor and a same word line, the plurality of transistors are all coupled to a bit line, and memory cells located in a same row are coupled to a same plate line. The method includes: in a first sub-phase of an active phase, conducting, through an unselected word line, a transistor coupled to the unselected word line, applying a first voltage V1 to the bit line, and applying a second voltage V2 to an unselected plate line; and in a second sub-phase of the active phase, conducting, through a selected word line, a transistor coupled to the selected word line, applying a third voltage V3 to the bit line, and applying a fourth voltage V4 to a selected plate line, where |V4-V3|=Vw, |V4-V1|<1/2Vw, and |V3-V2|<1/2Vw. An amplitude of an interference voltage is reduced by reducing a voltage difference between two ends of an unselected memory cell, to resolve a problem of high refresh frequency.