Burst Strobe Read Path Clocking for Low-Jitter SDRAM Reads
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Solution Overview
Problem
Existing synchronous dynamic random-access memory (SDRAM) technologies, particularly GDDR6 and GDDR7, suffer from issues such as jitter accumulation and latency due to the use of local PLL clocks, leading to reduced data transfer rates and increased bit error rates (BER) during high-speed operations.
Innovation Solution
Implementing a burst strobe read path clocking circuit that uses a differential RCK strobe synchronized with the WCK clock, incorporating a phase interpolator and glitch-free clock multiplexer to maintain synchronicity and track voltage drift, ensuring the clock tree operates at full rate even during burst modes without re-training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If local PLL clocks are used for read path clocking, then clock distribution is simplified, but jitter accumulation increases and data transfer rates decrease
Solution Approach 1:
The patent introduces a strobe signal as an intermediary between the clock source and the read path sampling. The strobe-based clocking circuitry receives the strobe signal and generates clock signals for the read path, acting as a mediator that eliminates jitter accumulation while maintaining clock distribution simplicity. This intermediary approach allows the system to achieve high-speed data transfer without the jitter issues associated with direct PLL clocking.
2Device complexity
If local PLL clocks are used, then clock generation is straightforward, but latency increases during high-speed operations
Solution Approach 1:
The patent implements continuous voltage tracking through the strobe-based clocking circuitry, which maintains synchronicity between the clock signal and data signals during high-speed operations. This continuous tracking eliminates the latency that would otherwise occur during voltage drift corrections, ensuring uninterrupted high-speed data transfer without increasing clock generation complexity.
3Productivity
If burst mode operation is implemented, then data transfer speed increases, but re-training requirements increase bit error rates
Solution Approach 1:
The patent incorporates feedback mechanisms in the strobe-based clocking circuitry that continuously monitor and adjust clock signals during burst mode operations. This feedback ensures that voltage drift is tracked and corrected in real-time, preventing the re-training requirements that would otherwise increase bit error rates during high-speed burst transfers.
4Reliability
If continuous voltage tracking is implemented, then synchronicity is maintained, but circuit complexity increases
Solution Approach 1:
The strobe-based clocking circuitry is designed to perform multiple functions: it generates clock signals, tracks voltage drift, maintains synchronicity, and operates in both continuous and burst modes. By making the circuit multi-functional, the patent achieves continuous voltage tracking and synchronicity maintenance without proportionally increasing circuit complexity, as the same circuit elements serve multiple purposes.
Data Source
AI summary
Embodiments included herein are directed towards burst strobe read path clocking circuits and methods of using the same. Embodiments may include strobe-based clocking circuitry configured to receive an output from phase locked loop circuitry and an output from a memory controller. Embodiments may further include clock tree circuitry configured to receive an output from strobe-based clocking circuitry and provide feedback to the strobe-based clocking circuitry. Embodiments may also include slice circuitry configured to receive an output from the clock tree circuitry, wherein a plurality of modes of operation are simultaneously enabled.