DDR5 Signal Sampling Circuit for Accurate NT ODT Command Decoding
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Solution Overview
Problem
In DDR5 DRAM, erroneous decoding of Non-Target On-Die Termination Command (NT ODT CMD) signals occurs due to the chip select signal being at a low level in two consecutive clock cycles, leading to incorrect interpretation of command signals.
Innovation Solution
A signal sampling circuit with a clock processing circuit, chip select control circuit, and output sampling circuit is employed to perform two-stage sampling and logical operations on chip select signals, ensuring accurate decoding of both 2T CMD and NT ODT CMD signals by using previous clock cycle samples for logical checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the chip select signal is monitored in a single clock cycle, then the decoding speed is maintained, but erroneous decoding occurs when the signal remains low across consecutive clock cycles
Solution Approach 1:
The patent applies preliminary action by performing two-stage sampling where the first stage captures the chip select signal in advance, storing it in a register before the second stage performs the actual decoding sampling. This preliminary capture allows the system to check the signal state from the previous clock cycle and prevent erroneous decoding when the signal remains low across consecutive cycles, thereby improving reliability without significantly increasing overall system complexity.
2Reliability
If two-stage sampling is performed on the chip select signal, then erroneous decoding is prevented, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the chip select signal sampling process into two distinct stages: a first sampling stage that captures the signal state in advance and stores it in a register, and a second sampling stage that performs the actual decoding operation. This segmentation allows the system to compare the current signal state with the previously captured state, preventing erroneous decoding while organizing the circuit logic into manageable, modular components that reduce overall complexity.
Solution Approach 2:
The first sampling stage performs preliminary action by capturing and storing the chip select signal state before the decoding operation occurs. This preliminary capture enables the system to detect when the signal remains low across consecutive clock cycles and prevent erroneous decoding in the second stage, thereby improving reliability with controlled complexity increase.
3Productivity
If the chip select signal is sampled without logical operation with previous cycle samples, then the processing speed is maintained, but decoding errors occur in the second clock cycle
Solution Approach 1:
The patent applies feedback by taking the output of the first sampling stage and feeding it back as a reference for the second sampling stage. The stored chip select signal state from the previous clock cycle is compared with the current signal state through logical operations, providing feedback that enables the system to detect and prevent erroneous decoding when the signal remains low across consecutive cycles, thereby improving NT ODT CMD signal decoding accuracy without significantly impacting processing speed.
Data Source
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AI summary
A signal sampling circuit and a semiconductor memory are provided. The signal sampling circuit comprises: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal. In this way, the signal sampling circuit may enhance the accuracy of command decoding.