3D Two-Transistor Memory Cell Tiers for Higher Density
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints when shrinking memory cell size.
Innovation Solution
A memory device with stacked tiers of two-transistor memory cells, utilizing separate conductive access lines and shared data lines, along with a charge storage structure, to improve device area efficiency and reduce capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then storage density is improved, but fabrication constraints and physical limitations make it difficult to achieve further shrinkage
Solution Approach 1:
The patent transitions from a planar memory cell arrangement to a three-dimensional stacked architecture with multiple tiers. Each tier contains memory cells that are vertically stacked above one another, utilizing the vertical dimension to increase storage density without further shrinking the lateral footprint of individual cells. This dimensional change allows more memory cells to be packed into a given device area while avoiding the fabrication constraints associated with lateral scaling.
2Quantity of substance
If conventional memory cell structures are used, then fabrication is simpler, but storage density cannot be increased further
Solution Approach 1:
The memory device is divided into multiple tiers, with each tier containing a subset of memory cells. This segmentation allows the complex three-dimensional structure to be constructed systematically, with each tier being formed through separate fabrication processes. The segmentation also enables independent optimization of each tier's memory cell structure while maintaining overall device functionality.
Solution Approach 2:
The patent implements a nested structure where memory cells in upper tiers are positioned above and around memory cells in lower tiers. The conductive structures and charge storage elements are nested within the vertical stack, with each component carefully positioned to minimize interference between adjacent cells while maximizing space utilization. This nesting approach increases storage density without proportionally increasing device complexity.
3Area of stationary object
If data lines are placed close together to reduce area, then area efficiency is improved, but capacitive coupling between adjacent data lines increases
Solution Approach 1:
The patent separates data lines into different vertical tiers, placing them at different heights above the substrate. This vertical separation in the third dimension reduces capacitive coupling between adjacent data lines that would otherwise be close together in the same plane. The staggered arrangement allows data lines to be densely packed in the lateral direction while maintaining electrical isolation through vertical spacing.
Solution Approach 2:
The patent introduces dielectric layers and insulating structures as intermediaries between adjacent data lines in different tiers. These intermediary layers act as electrical barriers that reduce capacitive coupling while allowing the data lines to be positioned close together for area efficiency. The intermediary structures enable dense packing without the harmful electrical interaction that would occur without them.
Data Source
AI summary
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.