Receiver Circuit Variable Delay for ISI Setup Margin

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Solution Overview

Problem

In semiconductor devices, the synchronization between data and data strobe signals can be disrupted due to inter-symbol interference (ISI), leading to a decrease in the setup margin for generating internal data, especially at high speeds where the frequency of the clock signal is high.

Innovation Solution

A receiver circuit is designed with a delay circuit that variably delays the data strobe signal based on a delay select signal, ensuring that the rising edge of the delayed data strobe signal aligns with the center of the data duration, thereby maintaining synchronization and securing a sufficient setup margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is sampled in synchronization with the rising edge of the data strobe signal at high speeds, then the data transmission rate is improved, but the setup margin for generating internal data decreases due to inter-symbol interference

Engineering Contradiction:
Improvedata transmission rateVSAvoidsetup margin
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies dynamics by making the delay amount of the data strobe signal variable rather than fixed. The delay circuit adjusts the delay amount dynamically based on the data pattern to compensate for inter-symbol interference variations, allowing the system to maintain reliable synchronization at high transmission rates.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of delay amount from a fixed value to a variable value that depends on the data pattern. By adjusting the delay amount parameter according to different data patterns, the system compensates for inter-symbol interference and maintains adequate setup margin while operating at high transmission rates.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the data strobe signal is delayed to align with data center, then synchronization is improved, but the circuit complexity increases due to variable delay control

Engineering Contradiction:
Improvesynchronization precisionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the delay control into discrete delay amounts corresponding to different data patterns. Instead of implementing a continuously variable delay, the system divides the delay adjustment into specific segments or steps, each optimized for particular data patterns, thereby reducing circuit complexity while maintaining synchronization precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements self-service by automatically selecting the appropriate delay amount based on the detected data pattern without requiring external intervention. The delay control circuit autonomously adjusts the strobe signal timing according to the data characteristics, simplifying the overall control architecture while achieving precise synchronization.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10311924B2Receiver circuit, and semiconductor device and system including the same
Publication Date: 2019.06.04 SK HYNIX INC
  • US10311924B2 patent drawing
  • US10311924B2 patent drawing
  • US10311924B2 patent drawing

AI summary

A receiver circuit may be provided. The receiver circuit may include a delay circuit and a synchronization circuit. The delay circuit may variably delay a data strobe signal based on a delay select signal. The synchronization circuit may generate internal data from data in synchronization with the variably delayed data strobe signal.