Memory Mat Column Layout for Uniform Sense Amplifier Regions
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Solution Overview
Problem
In semiconductor memory devices with memory cell arrays divided into memory mats, redundant memory mats with smaller column sizes lead to insufficient sense amplifier regions, compromising circuit characteristics.
Innovation Solution
Reconfigure the memory cell array by redistributing bit lines from normal column planes to a mixed column plane, ensuring equal column sizes and amplifier region dimensions across all planes, including a redundancy region for spare bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a redundant memory mat with spare bit lines is added to substitute defective bit lines, then reliability is improved, but the sense amplifier region size becomes insufficient and circuit characteristics deteriorate
Solution Approach 1:
The memory cell array is divided into multiple memory mats (first through fourth memory mats), each with its own sense amplifier region. The redundant memory mat is segmented as a separate entity with dedicated spare bit lines, allowing independent sizing and optimization of sense amplifier regions for each memory mat without compromising overall reliability.
Solution Approach 2:
The patent combines normal bit lines and spare bit lines into a unified column structure where both types of bit lines share the same sense amplifier region. This merging allows the sense amplifier region to service both functional and redundant bit lines, ensuring adequate sizing while maintaining defect substitution capability.
2Device complexity
If the column size of the redundant memory mat is made smaller than other memory mats, then device complexity is reduced, but the sense amplifier region characteristics become insufficient
Solution Approach 1:
Each memory mat is assigned specific bit lines with localized sense amplifier regions optimized for that mat's requirements. The redundant memory mat's sense amplifier region is locally optimized to handle both normal and spare bit lines, ensuring adequate characteristics while maintaining different column size configurations across memory mats.
Solution Approach 2:
The sense amplifier regions are designed to universally service both normal bit lines and spare bit lines within each memory mat. This multi-functionality allows a single sense amplifier region to handle multiple bit line types, ensuring consistent characteristics across different memory mat configurations without requiring uniform column sizes.
Data Source
AI summary
An apparatus that includes a plurality of first memory mats each including a plurality of common column sections except for at least one associated column section, the at least one associated column sections being selected by respective column addresses which are different from one another; and a second memory mat including the at least one corresponding column sections therein.