DRAM Refresh Scheduling With Programmable Bank Group Staggering

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Solution Overview

Problem

Memory devices, particularly DRAM, face inefficiencies in refresh operations, leading to reduced availability for reading and writing data due to staggered refresh operations that lock memory banks, causing idle periods and increased power consumption.

Innovation Solution

Implementing programmable refresh orders and stagger times for memory bank groups, allowing selective execution of commands on idle banks during refresh operations, thereby increasing the availability of memory banks for data access.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If staggered refresh operations are performed on memory banks, then data retention is maintained, but memory bank availability for reading and writing data is reduced

Engineering Contradiction:
Improvedata retentionVSAvoidmemory bank availability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory system is divided into multiple memory bank groups (first bank group, second bank group, third bank group) that can be refreshed independently. This segmentation allows different bank groups to be in different states (refreshing vs. accessible) simultaneously, maintaining data retention for all banks while keeping some banks available for data operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The refresh operation timing is made dynamic and programmable through the stagger time parameter. Different bank groups can be refreshed at different times according to a programmable sequence, allowing the system to adapt refresh scheduling to workload requirements and maximize memory availability while ensuring data retention.

Inventive Principle:
Principle #15Dynamics

2Reliability

If refresh operations are performed on memory banks, then data corruption is prevented, but power consumption increases

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

By dividing the memory system into multiple bank groups that can be refreshed independently, the system performs refresh operations on only one bank group at a time. This reduces the peak power consumption compared to refreshing all banks simultaneously, while still preventing data corruption across the entire memory system through sequential refresh of all bank groups.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The refresh operations are performed periodically on different bank groups in a staggered sequence. This periodic action distributes the power consumption over time rather than concentrating it in a single refresh event, reducing instantaneous power demands while maintaining data integrity through regular refresh cycles.

Inventive Principle:
Principle #19Periodic action

3Reliability

If refresh operations lock memory banks, then refresh completeness is ensured, but idle periods increase

Engineering Contradiction:
Improverefresh completenessVSAvoididle periods
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory banks are segmented into multiple independent bank groups that can operate independently. While one bank group is locked for refresh operations to ensure completeness, other bank groups remain unlocked and accessible for data operations, eliminating idle periods and maintaining system productivity throughout the refresh cycle.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system maintains continuous useful action by allowing data operations to proceed on unlocked bank groups while refresh operations complete on locked bank groups. This parallel operation ensures that refresh completeness is achieved without creating system-wide idle periods, as other banks continue to serve data requests.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12537041B2Memory with programmable refresh order and stagger time
Publication Date: 2026.01.27 LODESTAR LICENSING GROUP LLC
  • US12537041B2 patent drawing
  • US12537041B2 patent drawing
  • US12537041B2 patent drawing

AI summary

Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.