Dummy Array Shorting Structure for Smaller 3D Memory Die
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Solution Overview
Problem
Existing 3D crosspoint memory devices face challenges in achieving small die sizes due to the need for space-efficient integration of control circuitry and dummy arrays, which affects the overall memory chip design.
Innovation Solution
The implementation of a shorting structure on a dummy array within the memory device, where conductive lines electrically connect dummy address lines in a daisy-chain pattern, allowing for efficient use of substrate space and reducing the die size by grounding unnecessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy arrays are included in the memory device to maintain array uniformity and enable proper control circuit operation, then the reliability and functionality of the memory device are improved, but the die size increases due to the additional space required for dummy address lines and control circuitry
Solution Approach 1:
The patent extracts and removes the unnecessary portions of dummy address lines by identifying which dummy lines are not needed for proper device operation and eliminating them, thereby reducing die size while maintaining the essential functionality of the dummy array
Solution Approach 2:
The patent segments the dummy array into functional and non-functional portions, allowing selective removal or modification of specific dummy address lines while preserving the essential dummy array structure needed for control circuit operation
2Adaptability or versatility
If space is allocated for control circuitry on the substrate, then the functionality and control capabilities of the memory device are improved, but the available area for memory arrays is reduced, impacting storage capacity
Solution Approach 1:
The patent designs the substrate and address line structure to serve multiple functions: the same infrastructure supports both active memory arrays and dummy arrays, allowing the control circuitry to operate uniformly across different array types without requiring separate dedicated structures
Solution Approach 2:
The patent applies different configurations of dummy address lines to different regions of the substrate based on local requirements, allowing control circuitry to be positioned and sized appropriately for each region while optimizing the overall layout to minimize impact on memory array area
Data Source
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AI summary
A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.