Magnetic Tunnel Junctions for Memory and Resistor Integration
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Solution Overview
Problem
Conventional semiconductor manufacturing methods require separate processing steps and larger surface areas for forming memory and resistor devices, leading to increased manufacturing time and cost, as well as lower integration density due to the use of traditional sheet type resistors.
Innovation Solution
The integration of Magnetic Tunnel Junctions (MTJs) in both memory and logic regions of a semiconductor device, formed in the same processing step and Inter-Metal Dielectric (IMD) layer, allowing MTJs to function as both memory storage units and resistors, with electrical coupling in series or parallel to provide multiple resistance values and higher integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processing steps are used for forming memory and resistor devices, then manufacturing precision can be maintained, but manufacturing time increases and integration density decreases
Solution Approach 1:
The patent combines the formation of memory devices and resistor devices into a single processing step. MTJs are formed in the same dielectric layer as both memory storage units and resistors, eliminating the need for separate processing steps and thereby increasing manufacturing throughput while maintaining precision through unified process control
Solution Approach 2:
The MTJ structure serves multiple functions simultaneously: it acts as both a memory storage unit and a resistor. This multi-functionality allows a single component type to fulfill different circuit roles, reducing the number of processing steps required and increasing integration density without sacrificing manufacturing precision
2Ease of manufacture
If traditional sheet type resistors are used, then ease of manufacture is maintained, but integration density decreases and surface area increases
Solution Approach 1:
The patent merges the resistor function into the same dielectric layer as memory devices, using MTJs that are formed simultaneously with memory structures. This integration eliminates the need for separate sheet type resistor layers, significantly reducing the surface area occupied by resistor elements while maintaining ease of manufacture through unified processing
Solution Approach 2:
The patent transitions from planar sheet type resistors to three-dimensional MTJ structures formed in dielectric layers. By utilizing the vertical dimension through stacked dielectric layers, the surface area is reduced while maintaining electrical resistance functionality, effectively moving the resistor implementation to another dimensional space
3Productivity
If MTJs are formed in the same processing step as memory devices, then integration density increases and manufacturing time decreases, but device complexity increases
Solution Approach 1:
The patent employs MTJs that can function as either memory storage units or resistors depending on their configuration and connection. This universality allows a single processing step to create multi-functional components, increasing integration density and manufacturing efficiency while managing complexity through standardized component design
Solution Approach 2:
The patent segments the MTJ structures into different functional configurations within the same dielectric layer. By segmenting the formation process into distinct functional zones (memory regions and logic regions with different MTJ configurations), the patent maintains process simplicity while achieving high integration density through systematic organization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost by eliminating extra processing steps and achieves higher integration density by utilizing MTJs as both memory and resistor devices, offering programmable resistance values for various applications.
Implementation Method 1
A typical MRAM cell may include a Magnetic Tunnel Junction (MTJ), which includes a pinned layer, a free layer, and a tunneling barrier layer between the pinned layer and the free layer. Depending on the directions of the magnetic moments of the pinned layer and the free layer in an MTJ, the MTJ may exhibit a high resistance or a low resistance
Data Source
AI summary
A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.