Semiconductor Memory Hierarchical Bit Line Current Amplifier Read Disturbance
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Solution Overview
Problem
Resistance change memories face challenges with high probability of read disturbance due to small current difference between write and read currents, leading to decreased read speed and accuracy.
Innovation Solution
A semiconductor memory with a hierarchical bit line structure that includes a block array with shared conductive lines and current amplifiers, which amplifies cell current to a high sense current, reducing latency and preventing read disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read current is decreased to avoid read disturbance, then the probability of mistaken write operation is reduced, but the read speed is decreased due to increased amplification time
Solution Approach 1:
A current amplifier is introduced as an intermediary component between the memory cell and the sense amplifier. The current amplifier boosts the small read current from the memory cell to a larger current level before it reaches the sense amplifier, enabling fast read operations without requiring the sense amplifier to spend excessive time amplifying very small currents. This intermediary amplification stage resolves the contradiction by allowing the read current to remain small (preventing read disturbance) while still achieving high read speed through the intermediate current boosting stage.
2Device complexity
If the memory cell uses a two-terminal structure with the same path for write and read current, then the device complexity is reduced, but the current difference margin between write and read current becomes small
Solution Approach 1:
The current path is segmented into separate write path and read path by introducing a write select transistor. The write current flows through a different path (through the write select transistor) compared to the read current path. This segmentation allows the write current to be much larger than the read current without affecting the simple two-terminal memory cell structure, thereby increasing the current difference margin while maintaining low device complexity.
3Measurement precision
If the read current is amplified by a sense amplifier, then the read current can be detected, but the amplification period increases and read speed decreases
Solution Approach 1:
The current amplifier serves as an intermediary amplification stage that boosts the read current before it reaches the sense amplifier. By performing preliminary amplification in the current amplifier, the sense amplifier receives a larger current signal that requires less amplification time, thereby reducing the overall amplification period and increasing read speed while maintaining accurate read current detection.
Data Source
AI summary
A semiconductor memory includes a first block array including first to n-th blocks (n is a natural number of 2 or more) arranged in a first direction, each of the first to n-th blocks including a first memory cell, a first conductive line extending in the first direction, and shared by the first to n-th blocks, first to n-th current amplifiers corresponding to the first to n-th blocks, the i-th current amplifier (i is one of 1 to n) including an input terminal and an output terminal, the input terminal of the i-th current amplifier being electrically connected to the first memory cell in the i-th block, the output terminal of the i-th current amplifier being electrically connected to the first conductive line, and a sense amplifier electrically connected to the first conductive line.