MRAM Cell Layout Using Multi-Level Bit Lines for Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of miniaturizing memory cells in MRAM layouts to accommodate more cells in a limited area while adhering to design rules, particularly in scaling bit lines, is a significant issue in the development of MRAM technology.
Innovation Solution
The MRAM layout design incorporates bit lines in different metal levels, allowing memory cells to be scaled without violating minimum design rules by connecting memory cells across multiple metal layers, with MTJs and bit lines in distinct levels, enabling efficient use of layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are placed in the same metal level to simplify routing, then routing complexity is reduced, but memory cell density decreases due to design rule limitations
Solution Approach 1:
The patent applies dimensionality change by moving bit lines from a single metal level to multiple metal levels (BL0 in metal level 1, BL1 in metal level 2). This vertical separation allows memory cells to be scaled down without violating minimum design rules, thereby increasing memory cell density while maintaining routing functionality.
2Quantity of substance
If memory cells are miniaturized to increase capacity, then memory capacity increases, but design rule compliance becomes difficult to maintain
Solution Approach 1:
By utilizing multiple metal levels for bit line routing, the invention creates additional spatial dimensions for layout design. This allows memory cells to be miniaturized and packed more densely while maintaining adequate spacing and compliance with minimum design rules through vertical separation of routing layers.
3Quantity of substance
If bit lines are separated into different metal levels to increase density, then memory cell density increases, but routing complexity increases
Solution Approach 1:
The bit line routing is segmented across different metal levels, with BL0 in metal level 1 and BL1 in metal level 2. This segmentation allows each bit line to be routed independently in its designated metal level, simplifying the overall routing architecture despite the multi-level implementation.
Solution Approach 2:
The invention resolves routing complexity by utilizing the vertical dimension (multiple metal levels) to separate bit line routing paths. This vertical separation eliminates the need for complex lateral routing around other structures, as each bit line has dedicated vertical access through vias to its corresponding metal level.
Data Source
AI summary
A MRAM layout is provided in the present invention, wherein each memory cell includes a first word line, a third word line and a second word line spaced apart on a substrate in order and extending in a first direction over active areas, a first MTJ in BEOL metal layers with one terminal connected to a second active area and another terminal connected to a first bit line, a second MTJ in the BEOL metal layer with one terminal connected to a third active area and another terminal connected to a second bit line, wherein the first bit line and the second bit line are in different metal levels of the BEOL metal layer, and a source line is connected to a first active area and a fourth active area.