SRAM Write Assist Circuit Power Optimization
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Solution Overview
Problem
Conventional SRAM technologies face challenges in reducing power consumption and improving write assist operations, leading to increased power consumption and area usage due to existing write assist circuits.
Innovation Solution
A power-saving write-assist circuit is introduced, which dynamically adjusts its strength based on the operational state of the bit cell and type of memory access, using a virtual power supply node to reduce power consumption during inactive states and assist writes by weakening pull-up transistors during active writes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write assist circuits are used to improve write operations, then writeability is enhanced, but power consumption increases
Solution Approach 1:
The patent implements a dynamic write assist mechanism where the strength of the write assist circuit is adjusted based on the operational state of the bit cell. During active writes, the write assist circuit is enabled to weaken pull-up transistors and facilitate data writing. During inactive states, the circuit is disabled or reduced in strength to minimize power consumption. This dynamic adjustment resolves the contradiction by providing strong write assistance only when needed, rather than continuously.
Solution Approach 2:
The patent changes the operational parameters of the write assist circuit based on bit cell state. The circuit transitions between different strength levels (fully enabled, partially enabled, or disabled) depending on whether the bit cell is being actively written to or is in a stable state. This parameter change allows the system to optimize between writeability and power consumption by matching circuit strength to actual operational requirements.
2Use of energy by moving object
If read current is reduced in half-selected bit cells to save power, then power consumption decreases, but read operation reliability may be affected
Solution Approach 1:
The patent applies local quality by differentiating the strength of read current reduction based on the specific bit cell's selection state. Half-selected bit cells (those on the same word line but different column) experience reduced read current to save power, while fully-selected bit cells maintain full read current for reliable data reading. This localized differentiation allows power savings in non-critical paths while preserving read reliability in critical paths.
3Use of energy by moving object
If a virtual power supply node is used to reduce power consumption, then power usage decreases, but circuit complexity increases
Solution Approach 1:
The virtual power supply node serves multiple functions: it acts as a power reduction mechanism during inactive states, provides write assist during active writes, and maintains bit cell stability during transitions. By consolidating these multiple functions into a single circuit element, the patent minimizes the increase in circuit complexity while achieving significant power consumption reduction and write assist capabilities.
Data Source
AI summary
A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.