XOR-Encoded Resistive Memory Array for Fast Data Access
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Solution Overview
Problem
Existing non-volatile memory devices have relatively low read and write speeds compared to volatile memory devices, and they require efficient methods to manage resistance values for accurate data storage and retrieval.
Innovation Solution
A non-volatile memory device that uses a memory array with N+1 resistive memory cells, where the resistance values are set based on an exclusive OR (XOR) encoding scheme to express a bit sequence, and a write encoder generates N+1 write signals to set these resistance values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If non-volatile memory devices use traditional storage methods, then data retention is achieved, but read and write speeds are relatively low
Solution Approach 1:
The patent changes the fundamental parameter representation from direct binary storage to XOR-encoded resistance value storage. By encoding N bits into N+1 resistance values using XOR relationships, the system achieves faster read/write operations while maintaining data retention through the non-volatile nature of resistive memory cells.
Solution Approach 2:
The patent segments the storage unit into N+1 resistive memory cells that work together to store N bits of data. Each cell contributes to multiple bit representations through XOR relationships, allowing parallel read/write operations across multiple cells to achieve higher overall speeds while maintaining data integrity.
2Manufacturing precision
If resistance values are set for accurate data storage, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent makes each resistive memory cell multi-functional by having it participate in multiple XOR relationships. Each cell can be part of different bit representations depending on the encoding, reducing the need for dedicated cells for each bit and simplifying the overall device structure while maintaining manufacturing precision.
Solution Approach 2:
The patent merges the functions of N separate binary storage units into N+1 resistive memory cells that work collectively. By combining their resistance values through XOR relationships, the system achieves accurate data storage with fewer independent components, reducing device complexity.
3Adaptability or versatility
If multiple resistance value combinations are used to express bit sequences, then adaptability is improved, but the number of resistance changes required increases
Solution Approach 1:
The patent performs preliminary XOR encoding of the N-bit data before writing to the resistive memory cells. This pre-processing step determines the optimal resistance value combination in advance, allowing the system to select the encoding that minimizes resistance changes and power consumption while maintaining adaptability to store any N-bit sequence.
Solution Approach 2:
The system uses feedback from the current resistance states of the N+1 memory cells to determine the optimal encoding strategy. By analyzing the existing resistance values, the system can choose write operations that minimize the number of resistance changes required, reducing power consumption while maintaining the ability to represent any bit sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables efficient data storage and retrieval by optimizing resistance value settings, reducing power consumption, and minimizing the number of resistance changes required, thus improving the overall performance of non-volatile memory devices.
Implementation Method 1
N+1 resistive memory cells expressing a bit sequence of N bits... resistance values of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are the same, and, when the bit value of the bit position is a second bit value, resistance values of adjacent memory elements corresponding to the bit position among the N+1 resistive memory cells are different
Data Source
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AI summary
A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.