Integrated Memory Assembly Vertical Stacking
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Solution Overview
Problem
Conventional memory architectures face challenges in efficient packing and real estate utilization of memory arrays due to the placement of sense amplifiers and wordline drivers, leading to suboptimal use of semiconductor space.
Innovation Solution
The proposed solution involves vertically stacking memory decks with control circuitry, including sense amplifiers and wordline drivers, directly under the memory arrays, allowing for tight packing and conservation of semiconductor real estate by subdividing circuitry amongst banks and sections with overlapping regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If sense amplifiers and wordline drivers are placed separately from memory arrays in conventional architectures, then circuit functionality is maintained, but semiconductor space utilization becomes suboptimal
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture where memory arrays and control circuitry are vertically separated onto different decks. This dimensional change allows both components to occupy optimal spaces without interfering with each other's layout, thereby improving space utilization while maintaining functional independence.
Solution Approach 2:
The integrated assembly is divided into distinct functional decks: memory decks containing memory arrays and a separate control deck containing sense amplifiers and wordline drivers. This segmentation allows each component to be optimized independently for its specific function while being integrated into a unified three-dimensional structure.
2Productivity
If memory arrays are tightly packed to increase density, then real estate utilization improves, but fabrication difficulty and error rates increase
Solution Approach 1:
By stacking memory arrays vertically on separate decks rather than packing them laterally, the patent achieves high density without increasing lateral crowding. This vertical arrangement maintains adequate spacing between arrays for fabrication while maximizing overall memory capacity per chip area.
Solution Approach 2:
Multiple memory arrays are nested vertically in a stacked configuration, with each array on its own deck. This nesting approach allows high-density packing while maintaining physical separation that facilitates manufacturing and reduces fabrication errors.
3Ease of manufacture
If global input/output lines are made shorter to reduce fabrication complexity, then manufacturing ease improves, but connectivity options are reduced
Solution Approach 1:
The patent utilizes vertical interconnects through the stacked deck structure to provide multiple connectivity paths. This three-dimensional routing enables short global input/output lines while maintaining flexibility, as signals can travel vertically between decks and laterally within decks to reach various memory arrays.
Solution Approach 2:
The control circuitry on the control deck acts as an intermediary between external inputs and the memory arrays on memory decks. This intermediate layer simplifies external connections while providing flexible internal routing to multiple memory arrays through the stacked architecture.
Data Source
AI summary
Some embodiments include an integrated assembly having a memory deck over a base, and having an array of memory cells along the memory deck. The array includes rows which extend along a row direction and columns which extend along a column direction. Wordlines are along the rows and digit-lines are along the columns. CONTROL circuitry is along the base and includes WORDLINE DRIVER circuitry coupled with the wordlines. The CONTROL circuitry is subdivided amongst banks. The banks are elongated along the row direction. Each of the banks is subdivided amongst a series of sections, with the sections being arranged in section rows which extend along the row direction. Each of the sections includes a series of patches, with the patches including INPUT/OUTPUT circuitry. The patches are arranged in groups, with the groups sharing portions of the WORDLINE DRIVER circuitry.