3D Memory Device Adaptive Program Verify Control Circuit
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Solution Overview
Problem
Conventional 3D memory devices face challenges in achieving fast programming times due to the use of fixed Program Verify (PV) start programming pulses for all memory cells in an ISPP group, leading to unnecessary program verify operations for slower memory cells.
Innovation Solution
A 3D memory device with a control circuit that applies a sequence of incremental step programming pulses and performs program verify operations starting from a predefined programming pulse. The control circuit determines an updated first programming pulse based on the final programming pulse of a reference memory cell, allowing for optimized program verify operations for subsequent memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If fixed Program Verify start programming pulses are used for all memory cells in an ISPP group, then the programming process is simple to implement, but programming time increases due to unnecessary program verify operations for slower memory cells
Solution Approach 1:
The control circuit performs a preliminary characterization phase to identify the final programming pulse for each target threshold voltage before actual programming operations. This preliminary information is stored and used to determine optimized PV start programming pulses, allowing subsequent programming operations to skip unnecessary verify steps and reduce overall programming time.
Solution Approach 2:
The patent transitions from fixed, static PV start programming pulses to dynamic, adaptive pulses. The control circuit adjusts the PV start programming pulse based on the identified final programming pulse from the characterization phase, creating a variable pulse scheme that adapts to different memory cell performance characteristics while maintaining systematic control.
2Productivity
If the PV start programming pulse is determined based on the fastest memory cell, then programming time is optimized for fast cells, but slower memory cells require unnecessary additional program verify operations
Solution Approach 1:
The patent applies different PV start programming pulses to different memory cells based on their individual characteristics. By using the identified final programming pulse from the characterization phase, each memory cell receives a customized programming sequence tailored to its specific performance, rather than applying a uniform pulse scheme designed for the fastest cell.
Solution Approach 2:
The control circuit uses feedback from the characterization phase results to adjust programming parameters. The identified final programming pulse from each memory cell's characterization is fed back into the programming algorithm, allowing the system to optimize subsequent programming operations based on actual measured performance rather than relying on worst-case or average assumptions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces programming times by avoiding unnecessary program verify operations for slower memory cells, thereby improving overall programming efficiency.
Implementation Method 1
a selected memory cell is programmed at a target logic level (or, equivalently, at a target threshold voltage) based on an ISPP ('Incremental Step Pulse Programming') technique. A sequence of incremental step programming pulses are applied to the selected memory cell
Implementation Method 2
A logic level is physically stored in each memory cell in the form of electric charge within the control region: a change of electric charge within the control region defines a corresponding change of a threshold voltage of the memory transistor. Such change of the threshold voltage determines, during a read operation of a selected memory cell, a corresponding modulation of a channel current through the memory transistor
Data Source
AI summary
A three-dimensional memory device according to the present technology is proposed. The three-dimensional memory device includes a plurality of memory cell strings each memory cell string including a plurality of memory cells, a plurality of word lines each one associated with respective memory cells of the plurality of memory cell strings arranged at a same vertical distance from the substrate, and a control circuit. The control circuit is configured to apply a sequence of incremental step programming pulses to a selected memory cell, perform program verify after applying a first programming pulse, and determine an updated first programming pulse based on a second programming pulse indicating that the selected memory cell has been programmed and perform the program verify operations starting from the updated first programming pulse for each subsequently-selected memory cell.