Read-Only Memories TRIZ Cases

Separate sense and bias circuits optimize capacitance values, reducing precharge time while stabilizing program voltages.

A pre-boost stage elevates channel voltage of selected cells to inhibit unintended programming.

A memory array applies differential source line voltages to suppress leakage current in unselected cells during read operations.

Segmentation and parameter changes resolve leakage interference during sensing, maintaining reliability at reduced feature sizes.

Staggering row and column circuit initialization via a delayed reset signal reduces peak surge current, shortening internal power supply setup time.

Multiple precharge steps reduce program disturbance in unselected cells while maintaining programming reliability and throughput.

Dynamic clock timing minimizes leakage losses in capacitive nodes while preventing dead zones in output currents of semiconductor integrated circuits.

Dynamic charge pump adjustment reduces power consumption and minimizes voltage ripple in flash memory systems.

A semiconductor die loops back test voltage signals internally to bypass high capacitance at input contacts.

Adjusts sensing voltage based on adjacent cell data states to reduce read errors caused by capacitive coupling between closely spaced bit lines.

Variable voltages discharge electrons from memory arrays during verify recovery operations to clear storage cells and stabilize bitlines.

A voltage regulator switches between multiple generation systems to maintain stable input levels.

A memory device integrates a built-in self-test controller to generate pattern data and compare sensed results directly within the circuit.

Programming pilot signals into unused memory bytes allows the controller to estimate read voltages, resolving inefficiencies from one-shot estimation methods.

Segmented E-Fuse switches decouple voltage sensing from forward drop, preventing unnecessary data backup triggers during acceptable input voltage levels.

A semiconductor memory device applies distinct source voltages to separate work and code storage blocks during programming operations.

A non-volatile memory system determines customized voltage sets based on measured threshold distributions for optimized storage operations.

A nonvolatile memory programming method charges word-line signal lines to a pass voltage during the operation.

A memory receiver circuit shifts data signals to a constant DC level using differential amplification and bias control.

A memory controller segments NAND flash writes into foggy and fine phases using SLC cache blocks to reduce required buffer volume.

A non-volatile memory device copies setting information into multiple cell array regions to determine valid initial configuration data.

A microprocessor-based feedback circuit adjusts reference current magnitude and polarity to match memory cell variations.

A bitline bias circuit stabilizes voltage supply to transistors using high voltage components and control logic.

A 3D memory control circuit determines updated programming pulses based on reference cell data to optimize verify operations.

Preliminary erase verification reads all memory cells before option bit access, compensating for unstable power-up voltages and inaccurate reference signals.

An adaptive memory-state partitioning scheme configures end NAND cells to store fewer bits than intermediate cells.

Interface device blocks internal channel to perform duty cycle correction, resolving accuracy and data transfer speed trade-offs.

A data pattern detecting device compares compressed input and reference data to identify specific patterns efficiently.

A semiconductor memory device counts clock pulses to measure leakage current in local word lines.

Unified voltage control prevents punch through damage and data loss during write operations.

Differential sensing compares data and reference voltages to increase output speed while reducing layout area in nonvolatile memory devices.

A controller selects target open regions based on health information to perform time-distributed refresh operations.

Partitioned NAND flash page buffers overlap ECC processing with data output to reduce read latency.

A semiconductor memory device applies differentiated program inhibit and allowable voltages to bit lines based on target state groups.

Control circuits select neighboring word lines to determine read voltages for nonvolatile memory cells.

A storage controller triggers a dummy read operation to heat a non-volatile memory device when temperature drops.

Applying distinct voltages to word lines based on PS diameter suppresses erased level variations and enhances operational reliability.