Semiconductor Memory Device Staggered Circuit Initialization
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Solution Overview
Problem
Conventional semiconductor memory devices experience increased setup time for internal power supply voltage due to surge currents generated during simultaneous initialization of row and column path circuits, which adversely affects device performance.
Innovation Solution
Initializing the row path circuit and column path circuit at different time points using a reset signal generating circuit that delays the power-up signal to generate a column reset signal, thereby reducing the peak surge current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the row path circuit and column path circuit are initialized simultaneously in response to a power-up signal, then the initialization process is simple and fast, but surge current is generated which increases the setup time of the internal power supply voltage
Solution Approach 1:
The patent divides the initialization process into two separate segments: row path circuit initialization and column path circuit initialization. These are executed at different time points rather than simultaneously, which prevents the generation of surge current while still achieving complete initialization of both circuits.
Solution Approach 2:
The patent implements preliminary action by initializing the row path circuit first in response to the power-up signal, and then subsequently initializing the column path circuit in response to a column reset signal. This sequential preliminary initialization avoids simultaneous activation that causes surge current.
2Object-generated harmful factors
If the row path circuit and column path circuit are initialized at different time points, then the peak surge current is reduced, but the initialization process becomes more complex
Solution Approach 1:
The patent introduces a reset signal generating circuit as an intermediary component that manages the sequential initialization process. This circuit generates the column reset signal at the appropriate time to initialize the column path circuit after the row path circuit, thereby reducing peak surge current while maintaining controlled complexity through a dedicated control mechanism.
Data Source
AI summary
A semiconductor memory device includes a row path circuit, a reset signal generating circuit and a column path circuit. The row path circuit is initialized in response to a power-up signal. The reset signal generating circuit delays the power-up signal to generate a column reset signal. The column path circuit is initialized in response to the column reset signal. The semiconductor memory device can reduce a peak value of a surge current by initializing a row path circuit and a column path circuit at different time points. Therefore, the semiconductor memory device may have a relatively short setup time of an internal power supply voltage.