Adaptive Memory State Partitioning for NAND Flash End Cell Errors
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Solution Overview
Problem
NAND flash memory cells adjacent to the ends of a string are susceptible to errors due to program disturb, which existing techniques struggle to fully mitigate, especially with the increased issues from shrinking word line spacing and GIDL effects.
Innovation Solution
An adaptive memory-state partitioning scheme is implemented, where memory cells at the ends of a NAND string store fewer bits than the rest, allowing for a sufficient margin to overcome errors, and in some embodiments, additional memory cells are added to maintain capacity while reducing GIDL-induced errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells at the ends of a NAND string store the same number of bits as other cells, then memory capacity is maximized, but program disturb errors increase due to GIDL effects and shrinking word line spacing
Solution Approach 1:
The patent applies local quality by differentiating the storage capacity of end memory cells from intermediate memory cells. Specifically, end memory cells (adjacent to select gates) are configured to store fewer bits (e.g., 1 bit) compared to intermediate memory cells (e.g., 2 bits), thereby reducing GIDL-induced errors in vulnerable end positions while maintaining high capacity in the majority of the string.
Solution Approach 2:
The patent segments the NAND string into distinct regions: end memory cells and intermediate memory cells. This segmentation allows independent configuration of storage capacity in each region, enabling the system to optimize for both reliability (in end cells) and capacity (in intermediate cells) simultaneously.
2Quantity of substance
If word line spacing is reduced to increase memory density, then memory capacity increases, but program disturb errors worsen due to increased GIDL effects
Solution Approach 1:
The patent addresses GIDL effects caused by reduced word line spacing by applying local quality protection to end memory cells. These cells experience the most severe GIDL effects due to their position near select gates, so they are configured with reduced storage capacity (e.g., 1 bit instead of 2 bits), creating a margin that compensates for the increased error rate from aggressive scaling.
3Reliability
If end memory cells store fewer bits, then program disturb errors are reduced, but overall memory capacity decreases
Solution Approach 1:
The patent minimizes the capacity loss from reduced end cell storage by segmenting the NAND string and recognizing that end cells represent a small fraction of the total. For example, in a 32-cell string, only 2 cells (6%) have reduced capacity, while 30 cells maintain full capacity, thereby preserving overall memory capacity while improving reliability at critical positions.
Data Source
AI summary
A NAND type flash memory is organized into NAND strings with each being a chain of memory cells in series and connected via select transistors on both ends of the string to either a bit line or a source line. The memory cells adjacent both ends of a NAND string are particularly susceptible to errors due to program disturb. An adaptive memory-state partitioning scheme is employed to overcome the errors, in which each memory cells are generally partitioned to store multiple bits of data, except for the ones adjacent both ends where relatively less bits are stored. In this way, the storage of relatively less bits in the memory cells adjacent both ends of a NAND string affords sufficient margin to overcome the errors. For example, in a memory designed to store 2-bit data, the cells adjacent both ends of a NAND string would each be configured to store one bit of the 2-bit data.