NAND Flash Page Buffer Partitioning for Read Speed
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Solution Overview
Problem
NAND flash memory devices face limitations in supporting high-speed code shadow and execute-in-place applications due to architectural, performance, and bad block issues, which hinder efficient data reading and processing.
Innovation Solution
Implementing a method that partitions the page buffer and cache register into multiple parts, allowing for concurrent ECC processing and data output, and utilizing a partition busy bit to manage the status of data processing, enabling faster and more efficient data reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional sequential ECC processing is used for the entire page buffer, then data integrity is ensured through complete error correction, but read speed deteriorates due to the time-consuming nature of ECC processing
Solution Approach 1:
The page buffer is divided into multiple partitions (first part and second part), allowing ECC processing to be performed on one partition while data from another partition is being output. This segmentation enables parallel processing of different data portions, reducing the total time required for ECC processing and improving read speed.
Solution Approach 2:
ECC processing is initiated for the first part of the page buffer while the second part is being prepared for output. This preliminary action allows the ECC processing to overlap with the data output phase, effectively hiding the ECC processing time within the overall read operation and improving perceived read speed.
2Productivity
If the page buffer is partitioned and ECC processing is performed on one part while outputting data from another, then read performance is improved through overlapping operations, but device complexity increases due to additional control logic
Solution Approach 1:
The page buffer is divided into multiple partitions (first part and second part), allowing ECC processing to be performed on one partition while data from another partition is being output. This segmentation enables parallel processing of different data portions, reducing the total time required for ECC processing and improving read speed.
Solution Approach 2:
A partition busy bit is introduced as an intermediary control mechanism to manage the status of each partition. This simple binary indicator allows the control logic to track which partitions are currently being processed, enabling complex parallel operations to be coordinated through simple status checking and clearing, thereby managing complexity.
3Productivity
If a partition busy bit mechanism is implemented to manage concurrent operations, then operational efficiency is improved through better resource management, but ease of operation deteriorates due to additional status tracking requirements
Solution Approach 1:
The partition busy bit mechanism operates automatically without requiring external intervention. When ECC processing is initiated for a partition, the corresponding busy bit is automatically set. When the processing completes, the bit is automatically cleared. This self-service approach simplifies operation by eliminating the need for manual status tracking while maintaining efficient resource management.
Data Source
AI summary
A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.