Semiconductor Memory Reading Margin via Preliminary Erase Verification
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Solution Overview
Problem
During power-up, the bandgap reference (BGR) circuit in semiconductor memory products provides unstable supply voltage, leading to inaccurate reference voltages, which can result in errors when reading option bits or status bits due to the charge pump circuit's inability to generate a predetermined reading voltage.
Innovation Solution
A semiconductor memory apparatus comprising a memory cell array, a switch circuit, and a sensing circuit, where the sensing circuit receives simultaneous reading currents from multiple memory cells through the switch circuit during a read operation, allowing for correct reading of option bits or status bits even if the reading voltage does not reach the target value by summing the currents to increase the margin of the read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the BGR circuit is used to generate reference voltage during power-up, then a stable voltage source is provided, but the reference voltage is inaccurate because the supply voltage is unstable
Solution Approach 1:
The patent applies preliminary action by performing an erase verification operation before the main read operation during power-up. This preliminary verification reads all memory cells in the mini-array to ensure they are properly erased before attempting to read the option bits or status bits, compensating for the unstable reference voltage conditions during initial power-up.
2Ease of operation
If the charge pump circuit generates reading voltage based on unstable reference voltage, then power-up operation can proceed, but the reading voltage does not reach the target value
Solution Approach 1:
The patent performs a preliminary erase verification read operation before the actual option bit read operation. This preliminary action allows the system to proceed with power-up while accounting for the fact that the reading voltage may not have reached its target value yet, as the verification read compensates for the voltage instability.
3Duration of action of stationary object
If the reading voltage does not reach the target value, then power-up can continue, but the reading current decreases causing read errors
Solution Approach 1:
The patent implements a preliminary erase verification operation that reads all memory cells before reading the option bits or status bits. This preliminary action ensures that even if the reading current is decreased due to unstable voltage, the verification read can detect and compensate for potential read errors by ensuring all cells are properly erased first.
Data Source
AI summary
A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.