Memory Controller SLC QLC Hybrid Write for Buffer Reduction
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Solution Overview
Problem
Current memory systems face challenges in efficiently managing data writes across multiple pages in NAND flash memory, particularly in reducing buffer capacity requirements and ensuring data integrity during power shutdowns.
Innovation Solution
The memory system employs a controller that uses a combination of single-level cell (SLC) and quad-level cell (QLC) programming, where data is initially written in cache blocks using SLC programming and then transferred for QLC programming, allowing for reduced buffer memory needs and ensuring data integrity by separating foggy and fine write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written directly to NAND flash memory blocks, then write speed is improved, but buffer capacity requirements increase and data integrity during power shutdowns is compromised
Solution Approach 1:
The patent segments the write operation into two distinct phases: foggy write (initial rapid write) and fine write (precision write). This segmentation allows the controller to first quickly write data to cache blocks using SLC programming, then later complete the precise write to the target QLC blocks, thereby reducing buffer requirements while maintaining write speed.
Solution Approach 2:
The controller performs preliminary action by writing data to cache blocks during the foggy write phase before the fine write phase. This preliminary write to intermediate cache blocks allows the controller to release buffer memory early while ensuring data can be completed later with proper verification, thus reducing buffer capacity needs.
2Speed
If data is written directly to NAND flash memory blocks, then write speed is improved, but data integrity during power shutdowns is worsened
Solution Approach 1:
The patent implements beforehand cushioning by introducing cache blocks as an intermediate buffer between the controller and target blocks. During power shutdowns, data resides safely in these cache blocks during the foggy write phase, providing a cushion that prevents data loss. The subsequent fine write phase then transfers data from cache blocks to target blocks with verification, ensuring data integrity.
Solution Approach 2:
The cache blocks serve as an intermediary between the controller and target QLC blocks. This intermediary structure allows the controller to write data quickly to cache blocks during foggy write, then later complete the transfer to target blocks during fine write with proper verification, thus maintaining both speed and data integrity.
3Speed
If SLC programming is used for all writes, then write speed is improved, but memory capacity and cost increase
Solution Approach 1:
The patent applies local quality by using SLC programming only for the foggy write phase to cache blocks where speed is critical, then switching to QLC programming for the fine write phase to target blocks where capacity efficiency is prioritized. This localized application of different programming modes optimizes both speed and capacity utilization.
Solution Approach 2:
The patent implements dynamics by dynamically switching between SLC and QLC programming modes based on the write phase. During foggy write, SLC mode is used for speed; during fine write, QLC mode is used for capacity efficiency. This dynamic adaptation allows the system to optimize performance characteristics according to operational requirements.
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.